2-Step algorithm for automatic alignment in wafer dicing process

In this study, automatic alignment algorithm was developed for wafer dicing. Dual inspection method was applied for wafer alignment. The algorithm was derived from inspection data and geometric relations on machine coordinate. The algorithm calculated compensation value which minimized x, y, θ errors. Control strategy was designed according to characteristics of each axis. In experiment, standard position was defined with golden device. When working device was put on stable, it was aligned and moved by compensation value. Alignment error were inspected to check accuracy and precision of the algorithm. Average error was sub-pixel level for y axis on vision coordinate.     

Iterative algorithm for automatic alignment by object transformation

Mathematical model for automatic alignment of wafers was derived under the assumption of the ideal condition of alignment marks. Because wafers were fabricated under non-ideal conditions at the factory level, the wafers were difficult to align during the manufacturing process. The errors from the distortion were reduced by repeated application of an ideal alignment sequence algorithm. The alignment algorithm, which was modified to be iterative, is based on the object transformation and is composed of matrix operations like a linear model. The convergence speed of the iteration could be varied by use the convergence constant η. The accuracy of the algorithm was demonstrated by a dicing machine used in an experiment. The alignment was repeated until the error was under the tolerance level of the inspection system. The convergence constant was varied to monitor its effect on iterative alignment speed. The result showed that this iterative algorithm was simple but accurate enough for application at the manufacturing level.     

划片机视觉识别系统设计原理分析

自动对准技术是集成电路后封装设备中的一项重要单元技术,是全自动划片机与普通划片机的最大区别之一。国际上主要划片机制造商的全自动设备都配有实时高效的图像识别对准单元。作为提高其设备性能的一种有力手段,长期以来在划片机的研制过程中我们已逐渐形成了适合划片机应用的视觉识别技术,取得了显著的阶段性成果。     

全自动晶圆划切设备之可靠性分析

介绍了半导体全自动晶圆划切设备的总体结构和功能以及提高可靠性的一些方法,通过采用这些方法,将整体系统内各部分彼此的关系用图示表现,进而以表示出来的关系计算出可靠性。     

ADT7100划片机的使用和维护

划片是电子器件封装工艺中重要的工艺之一,是将一整片晶圆切割成每个独立的个体,芯片切割的质量直接影响封装的质量和器件的性能。划片机有SAW类型的划片机,还有激光划片机。作者多年以来一直从事划片工艺,现对在用的ADT7100机器的结构、维修和维护作介绍,同时简单分析划片工艺。     

半导体封装领域的晶圆激光划片概述

介绍了半导体行业的发展,晶圆激光划片技术的特点、激光划片系统的组成与其在实际过程中应用。     

全自动划片机的关键技术研究

根据微电子工业的发展现状,论述发展全自动划片机的必要性;从全自动划片机的工作机理出发,分析空气静压电主轴、晶圆传输定位、自动对准、自动清洗等全自动划片机的关键技术;依据分析结果提出相应的解决措施。     

Aligned wafer bonding: A key to three dimensional microstructures

Successful fabrication of critically aligned three dimensional structures has been achieved by combining precision alignment procedures and techniques for direct silicon bonding. This produces three dimensional bonded layers that might include combinations of mechanical, electronic and/or optical elements formed in separate prefabricated layers. We call this techniquealigned wafer bonding. The precise aligned bonding of the features was done with an Optical AssociatesHyperline 400 Infrared Aligner. This machine can hold two imprinted wafers face to face while projecting an infrared image of the surfaces to a viewing screen. An array of alignment marks were etched into the surface of silicon wafers with hot potassium hydroxide. These V-grooves were then precisely aligned and the wafers were brought into contact for initial bonding. Subsequent high temperature annealing was used to strengthen and complete the chemical bonding. The instrumentation used in this work required alignment features with a vertical dimension of 30 micrometers to produce a suitable infrared image. We found that the apparent size of the images produced by the optical system limited the accuracy in precision alignment. However, with reduced wafer separation, we achieved wafer alignment with an accuracy of better than 5 micrometers. This technique would generally be used for the precision alignment and bonding of complementary micromechanical, electrical, or optical structures during the formation of three dimensional devices. The details of the aligned wafer bonding and its applications are presented.     

圆片等离子划片工艺及其优势

等离子划片是近年来兴起的一项新型圆片划片工艺。与传统的刀片划片、激光划片等工艺不同,该工艺技术可以同步完成一张圆片上所有芯片的划片,生产效率明显提升,是对现有划片工艺的一个颠覆。介绍了圆片划片工艺的工作原理、技术特点及其优势,并对其在解决圆片划片应用中的典型问题和不足之处进行了讨论。     

Advanced Dicing Technology for Semiconductor Wafer—Stealth Dicing

ldquoStealth dicing (SD)rdquo was developed to solve inherent problems of a dicing process such as debris contaminants and unnecessary thermal damages on a work wafer. A completely dry process is another big advantage over other dicing methods. In SD, the laser beam power of transmissible wavelength is absorbed only around focal point in the wafer by utilizing the temperature dependence of the absorption coefficient of the wafer. The absorbed power forms a modified layer in the wafer, which functions as the origin of separation in the separation process. In this paper, we applied this method for an ultra-thin wafer. The reliability of devices that is diced by SD was confirmed.     

分步投影光刻机对准系统应用与研究

分步投影光刻设备对准系统是由嵌在工作台上的一组基准标记、一套离轴对准系统和一套掩模对准系统组成。当工作台上的基准标记运行到投影镜头下面时,通过掩模对准系统在预定范围内扫描测量标记位置值。当工作台上的基准标记或硅片上的标记运行到离轴对准系统测量光束下面时,用系统扫描可以测量出标记的坐标值。即可通过测量值计算出每个曝光场的中心坐标值。通过EGA对准数据,可计算出硅片的平移偏移量、旋转量、比例量和正交性量的补偿值。     

全自动晶圆划片机软件系统的设计与实现

介绍了全自动晶圆划片机设备软件系统的设计与实现。根据设备自动化程度高,功能模块多、复用性强、耦合性强且复杂的特点,将软件系统按照层次化、模块化设计,并提出"二次封装"、界面脱离运动逻辑功能的思想。     

面向IC封装的视觉定位系统设计

以集成电路后道封装工序中的关键设备全自动砂轮划片机为例,详细阐述了面向IC封装的视觉识别定位系统的硬件结构和软件设计,在全自动砂轮划片机上开发了一套基于OpenCV视觉函数库的图像处理算法,控制划切工作台运动实现对IC工件划切街区的精确定位.在模板匹配方式上,该算法采用比较流行的边缘几何特征匹配方式,并在砂轮划片机的现...     

A hybrid wafer-dicing process for GaAs MMIC production

A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 μm across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges     

Technique for calibration of chassis components based on encoding marks and machine vision metrology

A novel technique for calibrating crucial parameters of chassis components is proposed,which utilizes the machine vision metrology to measure 3D coordinates of the center of a component’s hole for assembling in the 3D world coordinate system.In the measurement,encoding marks with special patterns will be assembled on the chassis component associated with cross drone and staff gauge located near the chassis.The geometry and coordinates of the cross drone consist of two planes orthogonal to each other and the staff gauge is in 3D space with high precision.A few images are taken by a highresolution camera in different orientations and perspectives.The 3D coordinates of 5 key points on the encoding marks will be calculated by the machine vision technique and those of the center of the holes to be calibrated will be calculated by the deduced algorithm in this paper.Experimental results show that the algorithm and the technique can satisfy the precision requirement when the components are assembled,and the average measurement precision provided by the algorithm is 0.0174 mm.     

乙醇辅助激光烧蚀切割硅晶圆工艺

为了减小激光切割硅晶圆时的热效应,选择去离子水作为辅助液体进行激光切割实验,研究了水下切割时激光烧蚀激发气泡对硅片表面造成的不良影响。为解决水下激光切割进程中诱导气泡大面积粘结在硅片表面的问题,提出了去离子水混入乙醇溶液的实验方案,分析了水下激光切割中激光参数和乙醇浓度对切割质量的影响。实验结果表明,采用乙醇溶液作为辅助介质能明显减少粘结气泡的数量,减轻气泡破溃冲击带来的负面影响。实验采用乙醇浓度5 wt.%时切割得到的硅片比纯水中切割得到的硅表面影响区减小50%以上、切缝宽减幅约20%,有效提升了激光切割质量。     

300-mm Low-${hbox {k}}$ Wafer Dicing Saw Development

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

视觉系统在硅片检测上的应用

机器视觉是利用机器代替人眼来做各种测量和判断.介绍了全自动硅片装片机中利用视觉系统对硅片的边缘进行检测,在线将有缺陷的硅片剔除,将完好的硅片送入下一个环节.大大降低了人工强度和碎片率,减少了人工与硅片的接触,避免了人为因素对硅片的污染,有效地提高了成品率.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.