An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

A 7-mask CMOS process with selective oxide deposition

A seven mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist is described. The process modules for self-aligned well and one-mask LDD formation are developed. The features of the process are: (1) short TAT (7 masks to first metallization), (2) self-aligned twin retrograde wells with 40% reduction of the p⁺-n⁺ spacing compared to conventional wells, and (3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFETs giving a 10% larger on-current for p-channel MOSFETs compared to a conventional process     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

Optimization of a self-aligned titanium silicide process forsubmicron technology

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi ₂ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n⁺ or n ⁺/p⁺ gate have demonstrated that the self-aligned process can be integrated in a 0.8-μm double-metal CMOS process     

A self-aligned retrograde twin-well structure with buried p+-layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

A self-aligned retrograde twin-well structure with buried p+-layer

The retrograde twin wells and buried p⁺ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n⁺-to-p⁺ spacing. It provides latch-up immunity at the 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stops     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Breakdown voltage enhancement of the p-n junction by self-aligneddouble diffusion process through a tapered SiO2 implant mask

The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO₂ implant mask. The p⁺-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p⁺ -p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V     

SATPOLY: a self-aligned tungsten on polysilicon process for CMOSVLSI applications

The use of complementarily doped n⁺ and p⁺ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated     

Experimental 0.1 μm p-channel MOSFET withp+-polysilicon gate on 35 Å gate oxide

Very-high-transconductance 0.1 μm surface-channel pMOSFET devices are fabricated with p⁺-poly gate on 35 Å-thick gate oxide. A 600 Å-deep p⁺ source-drain extension is used with self-aligned TiSi₂ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices     

Bipolar integrated Kelvin test structure for contact resistancemeasurement of self-aligned implantations

A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow n⁺ and p⁺ implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p⁺substrate and a retrograde n-well. Self-aligned TiSi2is formed on n⁺and p⁺diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n⁺poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.     

p-channel FET based on p/n double-quantum-well heterostructure

An experimental demonstration of a p-channel FET based on a heterostructure having vertically integrated p- and n-type quantum-well channels is discussed. The AlGaAs/GaAs heterostructure consists of a quantum well with an underlying p-region positioned above a second quantum well with an underlying n-region. The p-FET is fabricated with self-aligned p⁺ regions formed by zinc diffusion. Electrical characteristics for 1.5-μm gate lengths are nearly ideal in appearance with a maximum I_d of 90 mA/mm, a g _m of 80 mS/mm, and a g_m/g _d ratio of 140 at 77 K. The results demonstrate the viability of such stratified structures for the development of complementary integrated circuits or other circuits requiring integration of multiple device types     

100 Å-thick tunnel junction by double impurity doping liquid phase epitaxy for V-band TUNNETT oscillation

The tunnel injection transit time (TUNNETT) diodes with p⁺p⁺n⁺n⁻n⁺ structure were fabricated by liquid phase epitaxy (LPE). About 100 Å tunnel junction (p⁺n⁺) was successfully prepared by the double impurity diffusion of Ge and S during LPE growth. Continuous wave (CW) oscillation was realized at 51.520 GHz in the V-band cavity with the phase noise of −60 dBc/Hz at 1 kHz bandwidth.