A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A High-Performance Doubly-Balanced Mixer in 0.35-μm CMOS for Mode-1 MB-OFDM UWB Receivers

A new design of CMOS doubly-balanced down-conversion mixer intended for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) receiver of UWB group#1 bands and optimized for 0.35-μm technology is presented. The proposed mixer uses the current-bleeding technique in both the driver and switching stages with wideband impedance matching, consisting of a bandpass filter embedding the RF stage. The mixer performances are optimized for the AMS 0.35 μm CMOS process parameters. Over 3.1–4.8 GHz, the circuit drawing 6 mA from 3-V supply, shows a conversion gain of 14.0±1.0 dB, IIP3 of 0±2 dBm, doubly-sideband noise figure of 4.5–4.8 dB, and port-to-port isolation above 61.0 dB.

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

A 0.35μm CMOS Mixer for 2.45-GHz RFID Application

A RF mixer with both low noise and high linearity is designed,operating at 2.45-GHz ISM band for RFID application.The designed mixer uses an optimal input matching network and the carefully chosen sizes of transistors,also with the appropriate bias point,to improve the noise figure(NF).Also,with a resonant LC loop as the current source and a parallel PMOS-resistor as the load,the mixer has a high linearity.The post simulation results show that the single side- band noise figure of 8.57 dB,conversion gain of 10.02 dB,input 1-dB compression point(P-1dB)of-8.33 dBm,and input third-order intercept point(IIP3)of 5.35 dBm.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

20-GHz Differential Colpitts VCO in 0.35-μm BiCMOS

This work presents a differential Colpitts voltage controlled oscillator (VCO) with 8% tuning range at 20 GHz based upon the understanding on symbolic expressions of negative resistance and phase noise theory. Implemented in a 0.35-μm BiCMOS technology with f _T = 60 GHz, the VCO has an output power of −4.8 dBm. The lowest phase noise is −85 dBc/Hz, and −111 dBc/Hz at 100-kHz and 1-MHz offset, respectively. The power consumption of oscillator core is 34 mW under a −3-V supply. The chip only occupies an area of 370 μm × 610 μm. Moreover, a comparison between two topologies of Colpitts VCO shows that the proposed topology is prior to the conventional in high frequency applications.     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

High LO-RF isolation of zero-IF mixer in 0.18 μm CMOS technology

In this study, we introduce a zero-IF sub-harmonic mixer with high isolation in the 5 GHz band using 0.18 μm CMOS technology. Placing an LC-Tank between the class AB stage and the mixer core improves the isolation between the LO to RF at low supply voltage. The measured isolation is 48 dB between the LO and RF ports, and the 9.5 dB conversion gain is achieved with a supply voltage of 7 mA at 2.5 V. In order to alleviate the degradation of linearity due to the high conversion gain, we adopt the class AB stage as RF input stage. The measured IIP₃ is −7.5 dBm. This work was supported by National Science Council of Taiwan, ROC under contract no. NSC94-2220-E-005-002.     

Analog inner product operations for image compression in 0.35-μm CMOS

We propose a new model for analyzing the sensitivity of inner products to CMOS analog hardware implementation. It is derived from Spice simulations of the circuits to be implemented, and it is required for the design of analog image compression systems based on vector quantization at the focal plane of CMOS imaging sensors. The model is shown to be equivalent to a simpler and previously introduced theoretical model, if the errors caused by the fabrication process are around 6%. For 1.5% errors, the results differ from the theoretical predictions made by the previous model. Image compression results obtained with a prototype circuit fabricated in a 0.35-μm CMOS process are presented, and show close agreement with both theoretical and simulation predictions.     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.     

A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 μm CMOS

This paper describes a readout integrated circuit architecture for an infrared focal plane array intended for infrared network-attached video cameras in surveillance applications. The focal plane array consists of 352 × 288 uncooled thin-film microbolometer detectors with a pitch of 25 μm, enabling ambient temperature operation. The circuit features a low-noise readout path, detector resistance mismatch correction and a non-linear ramped current pulse scheme for the electrical biasing of the detectors in order to relax the dynamic range requirement of amplifiers and the ADC in the readout channel, imposed by detector process variation and self-heating during readout. The design is implemented in a 0.35-μm standard CMOS process and two versions of a smaller 32 × 32-pixel test chip have been fabricated and measured for evaluation. The latest test chip achieves a dynamic range of 97 dB and an input-referred RMS noise voltage of 6.4 μV yielding an estimated NETD value of 26 mK with f/1 optics. At a frame rate of 60 FPS the chip dissipates 170 mW of power from a 3.4 V supply.