Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such “compliant interconnects” are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100- $mu{hbox {m}}$ pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of $sim$ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.      

Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved     

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

Foreword Wafer-Level Packaging

The four papers in this special section focus on wafer-level packaging. The selected papers cover the state-of-the-art and future development trends for wafer level chip scale packages (WLCSPs) by the leading institutes and industries operating in this field.     

Impact of 5% NaCl Salt Spray Pretreatment on the Long-Term Reliability of Wafer-Level Packages with Sn-Pb and Sn-Ag-Cu Solder Interconnects

Understanding the sensitivity of Pb-free solder joint reliability to various environmental conditions, such as corrosive gases, low temperatures, and high-humidity environments, is a critical topic in the deployment of Pb-free products in various markets and applications. The work reported herein concerns the impact of a marine environment on Sn-Pb and Sn-Ag-Cu interconnects. Both Sn-Pb and Sn-Ag-Cu solder alloy wafer-level packages, with and without pretreatment by 5% NaCl salt spray, were thermally cycled to failure. The salt spray test did not reduce the characteristic lifetime of the Sn-Pb solder joints, but it did reduce the lifetime of the Sn-Ag-Cu solder joints by over 43%. Although both materials showed strong resistance to corrosion, the localized nature of the corroded area at critical locations in the solder joint caused significant degradation in the Sn-Ag-Cu solder joints. The mechanisms leading to these results as well as the extent, microstructural evolution, and dependency of the solder alloy degradation are discussed.     

超级CSP—一种晶圆片级封装

研究了圆片级芯片尺寸封装。使用再分布技术的圆片级封装制作了倒装芯片面阵列。如果用下填充技术，在再分布层里和焊结处的热疲劳应力可以减小，使倒装芯片组装获得大的可靠性。     

SOI全介质隔离与高频互补双极兼容工艺

ＳＯＩ材料的全介质隔离技术与高频互补双极工艺的结合是研制抗辐照能力强、频带宽、速度高的集成运算放大器的理想途径，从实验的角度提出了一种ＳＯＩ材料全介质隔离与高频互补双极工艺兼容的工艺途径。     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric

This letter demonstrates reduction in effective work function of tantalum-nitride (TaN) metal gate with erbium-oxide-doped hafnium oxide. We report that TaN effective metal-gate work function can be tuned from Si midgap to the conduction band to meet the work-function requirement of NMOSFETs by incorporating ErO in HfO₂ with an equivalent oxide thickness as low as 1.15 nm. Several other lanthanide-oxide doped hafnium oxides show similar characteristics.     

封装、互连、连接器组件

RFIndustries公司7-16DIN适配器套件RFIndustries推出RFA-4013适配器套件,据称可以在试验台上和现场方便地将N型设备桥接到7-16DIN接口上。这种泡沫衬里、拉链锁闭的套件包含六种适配器:RFD-1652-(27-16DIN针到7-16DIN孔R/A适配器);RFD1653-(27-16DIN孔到7-16DIN孔管状适配器);     

封装、互连、连接器组件

Advantech一体化工业机箱Advantech公司工业自动化部门推出用于工业自动化平台的ATM-4233一体化机箱。ATM-4233将LCD显示器、键盘、触控板、功能键、光标键和OSD控制整合在一个机架上。该机架集成了一个视频A/D板,以确保CPU卡可兼容至IntelPentium4、PentiumM(无风扇)和Celeron     

封装、互连、连接器组件

Sullins Electronics连接器符合RoHSSullinsElectronics公司发布了新的引脚,符合无焊接压配合的边缘卡连接器。压配合的边缘卡以高密度为特点。0.062的子板上有100的间距,且支持0.093t到0.125″厚的母板。规格说明包括工作温度范围(-65℃到+125℃),每个接触对最大插入力16oz。可以订购带或不带凹槽排列的元件,也可选择尾长。可以选择各种安装形式、喷镀和按键选择,也可以用户自主定制。批量订购该连接器的平均价格为每接触对0.53到0.83美元。TEKO公司OPTATIVE外壳TEKO推出“OPTATIVE”外壳,专为电子和电气元件的快速装配而设计…     

封装、互连、连接器组件

YesControls小型熔断器用卡座YesControls公司推出一种多用途、模块化保险丝座,用于小尺寸熔断器(保险丝),尺寸为3/32×11/2″,满足UL、CSA规定的30A@600VAC,这些卡座可以方便卡入35mm对称DIN轨上,保证工作安全、快速熔断器安装与更换。这些卡座使得多极安装更为方便,用户仅需储存单极部件即可。公司还提供一种待选、内置氖灯的熔断指示器,以简化故障排查,并减少设备停机时间。该产品带有前面板上回转开启铰链控制杆,以实现安全和方便地插入与取出熔断器,插入和更换时无需特殊工具。该卡座独设计特,提供很宽的熔断器表面接触面积,接…     

封装与互连

Samtec公司Micro Card插座 Samtec公司薄型高速MicroCard插座接口(SAL1系列)为串行ATA和其他高速子卡应用提供卡到板的连接.据称其速度高达3Gbps.这些成对使用的互连产品采用大偏移铍铜合金触点,间距为1mm.可匹配0.0625英寸厚或0.094英寸厚的板卡.     

晶圆级芯片尺寸封装技术

尺寸缩减几乎是电子封装技术应用的主要驱动力之一。高功能性和高可靠性与尺寸缩减的相互作用,也是所有微电子系统的决定因素。因此,最佳产品设计、最小单芯片封装和板技术的最佳结合,将提供最佳解决方案。晶圆级CSP将是匹配所有电子系统要求、降低总成本的单芯片封装技术的最佳方案。     

Wafer-Level Packaged Light-Emitting Diodes Using Photodielectric Resin

A large area $(hbox{1600} muhbox{m} times hbox{800} muhbox{m})$ high-brightness light-emitting diode (HB LED) employing rearranged metal pads and multipassivation layers is presented. To enlarge the active layer with a smaller mesa area and improve package productivity using large bonding pads, two electrodes were used to fabricate the LED; a primary electrode was in contact with the $n$, $p$-GaN as a conventional LED, and the second electrode was connected to the primary electrode with a passivation layer having photodielectric resin interposed between them. The LED was directly bonded to the metal-core printed circuit board without wire bonding or epoxy molding. The resultant HB LED has a low forward voltage ( $sim$3.2 V at 350 mA) due to the optimized $n$, $p$ -contact scheme, and an optical power of 75 mW with no encapsulation.