一种用于短距离器件的433/868 MHz的带I/Q校准的低中频接收机

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

纳米硅/单晶硅异质结MAGFET制作及特性

A MAGFET using an nc-Si/c-Si heterojunction as source and drain was fabricated by CMOS technology, using two ohm-contact electrodes as Hall outputs on double sides of the channel situated 0.7L from the source. The experimental results show that when VDS = -7.0 V, the magnetic sensitivity of the single nc-Si/c-Si heterojunction magnetic metal oxide semiconductor field effect transistor （MAGFET） with an L ： W ratio of 2 ： 1 is 21.26 mV/T, and that with an L ： W ratio of 4 ： 1 is 13.88 mV/T. When the outputs of double nc-Si/c-Si heterojunction MAGFETs with an L ： W ratio of 4 ： 1 are in series, their magnetic sensitivity is 22.74 mV/T, which is an improvement of about 64% compared with that of a single nc-Si/c-Si heterojunction MAGFET.     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

A 2.05 eV AIGaInP sub-cell used in next generation solar cells

An Al0.13GalnP sub-cell used as the top cell in the next generation of high efficiency multi-junction solar cells is fabricated. An efficiency of 10.04% with 1457.3 mV in Voc and 11.9 mA/cm2 in Isc was obtained. QE comparison was carried out to verify the influence of an O-related defect introduced by the high Al-content materials on the cell performance during MOCVD growth. Hetero-structures are employed to confirm the origin of the decreasing short circuit current density compared to a GalnP single junction solar cell. An effective method to improve the performance of broadband solar cells by increasing Isc with a cost of Voc was proposed.     

一种带有混合平均式分布采样电路的低功耗CMOS全折叠型模数转换器

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

Single-mode GaAs/AIGaAs quantum cascade microlasers

Single-mode edge emitting GaAs/AlGaAs quantum cascade microlasers at a wavelength of about 11.4μm were realized by shortening the Fabry-Perot cavity length. The spacing of the longitudinal resonator modes is inversely proportional to the cavity length. Stable single-mode emission with a side mode suppression ratio of about 19 dB at 85 K for a 150-μm-long device was demonstrated.     

欧姆接触金属退火对应力AlGaN/GaN异质结构中电子迁移率的影响

The influence of annealed ohmic contact metals on the electron mobility of a two dimensional electron gas （2DEG） is investigated on ungated AlGaN/GaN heterostructures and AlGaN/GaN heterostructure field effect transistors （AlGaN/GaN HFETs）. Current-voltage （I-V） characteristics for ungated AlGaN/GaN heterostructures and capacitance-voltage （C-V） characteristics for AlGaN/GaN HFETs are obtained, and the electron mobility for the ungated AlGaN/GaN heterostructure is calculated. It is found that the electron mobility of the 2DEG for the ungated AlGaN/GaN heterostructure is decreased by more than 50% compared with the electron mobility of Hall measurements. We propose that defects are introduced into the AlGaN barrier layer and the strain of the AlGaN barrier layer is changed during the annealing process of the source and drain, causing the decrease in the electron mobility.     

A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

一种10Gb/s具有周期性相位校准双沿触发CDR和CTLE/DFE组合均衡功能的接收端

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.     

SOI基蓝紫光敏感光电探测器的设计与模拟

According to Lambert’s law,a novel structure of photodetectors,namely photodetectors in siliconon-insulator,is proposed.By choosing a certain thickness value for the SOI layer,the photodetector can absorb blue/violet light effectively and affect the responsivity of the long wavelength in the visible and near-infrared region,making a blue/violet filter unnecessary.The material of the SOI layer is high-resistivity floating-zone silicon which can cause the neutral N type SOI layer to become fully depleted after doping with a P type impurity.This can improve the collection efficiency of short-wavelength photogenerated carriers.The device structure was optimized through numerical simulation,and the results show that the photodiode is a kind of high performance photodetector in the blue/violet region.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

A Tri-Port MIMO Antenna Designed for Micro/Pico Cell Applications with Self-Decoupled Structure

A tri-port MIMO antenna designed for Micro/Pico-Cell application is proposed. It is based on printed elements with X-shaped arms, which are oriented to 0°, 120° and 240° in the azimuth plane. The arms of these elements are connected, with which a selfdecoupled structure is formed. The mutual coupling between adjacent elements is below -15dB. Meanwhile, it size is compact and bidirectional radiation patterns with around 4dBi Gain and 92° 3dB beam width is achieved, which can provide good pattern diversity and full azimuth coverage in real applications.     

新型薄栅氧混合电压I/O缓冲器

This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS process.This mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer has.The design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ～34% with respect to the product of power consumption and speed.     

一种SFDR为83.5dB的14位100兆流水线模数转换器

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC）. The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

Impact of UV/ozone surface treatment on AIGaN/GaN HEMTs

Surface treatment plays an important role in the process of making high performance AlGaN/GaN HEMTs. A clean surface is critical for enhancing device performance and long-term reliability. By experimenting with different surface treatment methods, we find that using UV/ozone treatment significantly influences the electrical properties of Ohmic contacts and Schottky contacts. According to these experimental phenomena and Xray photoelectron spectroscopy surface analysis results, the effect of the UV/ozone treatment and the reason that it influences the Ohmic/Schottky contact characteristics of AlGaN/GaN HEMTs is investigated.     

基于标准CMOS工艺的1.5Gb/s单片集成光接收机

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.