A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Design of transmission and multiplexing systems for broadbandpacket networks

Dynamic time-division multiplexing (DTDM) is a flexible network transport technique capable of handling both continuous and bursty traffic effectively. By using three different multiplexing architectures in the network, DTDM permits graceful evolution of the existing circuit switching network into a flexible broadband packet communications network supporting integrated voice, data, and video traffic. The first multiplexing stage uses a packet assembler to multiplex different broadband services into a common DTDM-format serial bit stream. The second multiplexing stage uses a statistical packet multiplexer to concentrate network traffic for more efficient use of transmission facilities. The third multiplexing stage uses a synchronous time-division multiplexer for high-speed point-to-point transparent transmission. The multiplexer uses a simple tributary synchronization scheme based on positive and negative block justification, which combines the concept of controlled-slip and bit-stuffing techniques while maintaining information integrity. A generic CMOS LSI chip has been designed for use in the three-stage multiplexing system     

New CMOS Class AB Transmitter for 10 Gb/s Serial Links

This paper presents a new fully differential CMOS class AB transmitter for 10 Gb/s serial links. The transmitter consists of a fully differential multiplexer, a rail-to-rail configured pre-amplification stage, and a push-pull output stage. The multiplexer achieves a high multiplexing speed by using modified pseudo-NMOS logic where pull-up networks are replaced with self-biased active inductors. The rail-to-rail configured pre-amplification stage with active inductors amplifies the signals from the multiplexer. The fully differential output current is generated by a class AB output stage operated in a push-pull mode. High data rates of the transmitter are obtained by ensuring that the transistors in both the pre-amplification and output stages are always in saturation and the voltage swing of all critical nodes is small. The fully differential configuration of the transmitter effectively suppresses common-mode disturbances, particularly those coupled from the power and ground rails, the electro-magnetic interference exerted from channels to neighboring devices is also minimized. The transmitter minimizes switching noise by drawing a constant current from the supply voltage. The transmitter has been implemented in TSMC 0.18 μm 1.8 V 6-metal CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate that the transmitter provides a 5 mA peak-to-peak differential output current with 100 ps eye-width and >5 mA eye-height at 10 Gb/s. The transmitter consumes 18 mW with a total transistor area of 100 μm² approximately. Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995, and the M.A.Sc. degree in Electrical and Computer Engineering from Ryerson University, Toronto, Ontario, Canada in 2004. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. From 2002 to 2004, she was a research assistant and a M.A.Sc. student with the Microsystem Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. She is now with Intel Corp., CA. as an IC design engineer. Her research interests are in analog CMOS circuit design for high-speed data communications. Jean Jiang was awarded the Ontario Graduate Scholarship in 2003–2005 for academic excellence. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

A versatile ECL multiplexer IC for the Gbit/s range

A new approach to digital multiplexing for communication systems operating in the Gbit/s range is presented. With a single function, monolithically integrated in the established silicon bipolar process, many operations required by the communication system's multiplex equipment are achieved at data rates of up to 3 Gbits/s. The IC is a four-channel multiplexer designed to interface readily with ECL families. Demonstrations of the ICs performance include pseudorandom pattern generation by multiplexing ECL inputs up to 2 Gbits/s, demultiplexing into ECL registers at 1 Gbits/s, clock extraction in a 560 Mbit/s coaxial cable transmission system, and a modulo-n divider technique for timing generation using ECL feedback shift registers for frequencies up to 1.6 GHz. The demonstrations highlight the multiplexer's ability to effectively extend the system speed limit of commercially available ECL from a few hundred Mbits/s to the Gbit/s range. An eight-input multiplexer using three chips in a hybrid assembly is demonstrated multiplexing a static input pattern up to 2.8 Gbits/s.     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

光纤光栅和环行器构成的多路光分插复用器

讨论由光纤光栅和光环行器构成的光分插复用器的结构,性能和特点,提出采用一段刻有多个光纤布拉格光栅的光纤,两个光环行器,WDM复用器和解复用器等器件,构造能够对WDM的多个信道实施分插操作的光分插复用器,该光分插复用器的插入损耗要比简单地把多个单路的光分插复用器进行级联时小得多,波分复用全光网络中的光分插复用技术,是实现波分复用网络的关键技术之一。     

Diode Circuits for Pulse Regeneration and Multiplexing at Ultrahigh Bit Rates

Clocked step-recovery diode (SRD) circuits are investigated for regenerating and multiplexing PCM-type signals in the range from 0.1 to a few gigabits per second. One regenerator type is particularly suited for operating with signals in the 1-V range, whereas a differential version employing a magic T was developed for handling signals of down to about 5 mV. By making use of line transformers as coupling networks, high-level versions have been cascaded. Experiments performed at 0.3 and 1 Gbit/s yielded voltage amplifications (peak amplitudes) of 2.5-5.5 for single stages, and insertion power gains of 7-11 dB for 2-3 stage cascades. Diode stages have also been used for multiplexing 4 and 2 individual bit streams to give a combined output signal at 1 and 2 Gbit/s, respectively. In a preliminary multiplexer experiment an output at 4.5 Gbit/s was obtained. Finally, possibilities are discussed for improving the performance of the regenerators/multiplexers and for their applications.     

Extracted-Pole Filter Manifold Multiplexing

A transformation method is introduced for enabling filters of the extracted-pole variety to be match-multiplexed onto a manifold using standard waveguide multiplexer computer programs. Thus the advantages that accrue from the extracted-pole realization for filters may now be extended to multiplexers, which will be particularly useful in narrow-band high-power low-loss multiplexing applications. The measured performance of a 12-GHz contiguous-channel quadraplexer comprising TE/sub 011/ cavity extracted-pole elliptic filters is presented, demonstrating the very low insertion losses attainable with this form of realization. Since the majority of applications envisaged for this type of multiplexer is in high-power output circuitry, a discussion on thermal aspects is included.     

Long wavelength infrared 128×128 AlxGa1-xAs/GaAs quantum well infrared camera and imaging system

The authors discuss the development of a long-wavelength (8-14-μm) 128×128 Al_xGa_1-xAs/GaAs multiquantum well infrared (MQW IR) imaging system. Highly uniform, high-yield GaAs focal plane arrays, incorporating an integral grating structure for efficient optical coupling, were hybridized to CMOS multiplexers. Excellent imagery, with low noise, a noise equivalent differential temperature (NEΔT) of less than 10 mK, and a high image contrast signal-to-noise ratio, has been achieved. It is shown that figures of merit concerning array uniformity, such as yield, NEΔT, and maximum deliverable charge to the CMOS multiplexer are much more relevant variables that affect image quality than D*     

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optictransmission

We report a new integrated circuit for multiplexing and demultiplexing at rates of 100 Gb/s. In transistor multiplexer/demultiplexer circuits, the operating data rate is limited by transistor bandwidth. The demonstrated circuit, which uses terahertz Schottky diodes, readily attains the necessary bandwidths. The IC, based in the diode nonlinear-transmission line (NLTL) technology, consists of an array of four sample-hold gates driven by NLTL strobe generators. To permit use in multiplexing, the sample-hold gates use a six-diode configuration with 150 GHz output bandwidth. Initial measurements with simple data patterns at 104 Gb/s are demonstrated     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

Highly stable optical add/drop multiplexer using polarization beam splitters and fiber Bragg gratings

We demonstrate a novel wavelength-division add/drop multiplexer employing fiber Bragg gratings and polarization beam splitters. The multiplexer is easy to fabricate without any special technique such as UV trimming, and yet shows very stable performance with less than 0.3-dB crosstalk power penalty in a 0.8-nm-spaced, 2.5-Gb/s-per-channel wavelength-division multiplexing (WDM) transmission system.     

A DI/JI-compatible monolithic high-voltage multiplexer

A high-voltage multiplexer fabricated with both junction-isolated (JI) and dielectrically isolated (DI) D/CMOS process technologies is described in this paper. This eight-channel multiplexer is capable of switching a ± 50-V analog-signal range from a ± 60-V power supply. The switches exhibit less than 50 Ω of on-resistance and are capable of peak currents in excess of 0.5 A. An off-switch current model incorporating junction area and lifetime-dependent lateral DMOS drain-to-body and drain-to-substrate leakages is described. Elimination of the drain-to-substrate diode with dielectric isolation results in a factor of 15 reduction in leakage at 25°C and a factor of 10 improvement at 125°C, which agrees well with the model developed. Results show that the generation current from the space-charge region dominates device leakage at room temperature, while diffusion current from the neutral regions is predominant at elevated temperatures. In high-voltage testers, dielectrically isolated multiplexers offer the low leakage and high accuracy required by critical channels where less costly junction-isolated devices will not suffice.     

八路异步数据统计复接器设计

本文介绍了多路复接的基本原理,用具有最佳复用效率的统计复用方式设计了一个复合数据为同步／异步可选的八路异步数据复接器,该复接器具有４种工作方式：（１）复合数据为同步方式的疏数据复接;（２）复合数据为同步方式的发数据复接;（３）复合数据为异步方式的收数据复接;（４）复合数据为异步方式的发数据复接。工作方式灵活,可广泛用于卫星寻呼数据广播、低速数据采集、点对点数据传输等场合。     

用于SDH STM-4光发射机的4:1复接器和激光驱动器

采用CSMC0.6μm CMOS工艺设计实现了速率为622Mbps的4∶1复接器和激光二极管驱动器电路。4∶1复接器采用树型结构,由3个2∶1复接器组成。激光二极管驱动器电路由两级差分放大器和一级电流开关构成,级间采用源级跟随器隔离。电路芯片尺寸为1.5mm×0.7mm。电路采用单一正5V电压供电,功耗约为900mW。测试结果表明,电路的最高工作速率超过1.25Gbps速率,输出最大电流超过85mA。     

A novel ultracompact two-mode-interference wavelength division multiplexer for 1.5-/spl mu/m operation

A novel ultracompact 2/spl times/2 wavelength division multiplexer (WDM) for 1.55-/spl mu/m operation based on highly dispersive two-mode interference (TMI) was designed, theoretically modeled, and verified using a finite-difference-time-domain (FDTD) method. A two-moded waveguide assisted with a dispersive tooth-shaped grating provided a mode-dependent reflection band of central wavelength at 1.55 /spl mu/m. The wavelengths of 1538 and 1572 nm that were at the band edges and had the lowest reflection losses and relatively high dispersion were selected for wavelength multiplexing. The result showed that the wavelengths were separated by grating dispersion in a coupler length of 75 /spl mu/m which was much shorter than the required length of 1.1 mm in a regular TMI multiplexer of no grating. Insertion loss of about 1.7 dB and channel contrast of about 12 dB were achieved.     

Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS

A novel mm-wave phase modulating transmit architecture, capable of achieving data rates as high as 10 Gb/s is presented at 120 GHz. The circuit operates at a frequency of 120 GHz. The modulator consists of a differential branchline coupler and a high speed 4-to-1 analog multiplexer with direct digital input. Both a QPSK as well as a 8QAM constellation are supported. To achieve high output power, a 9-stage power amplifier is designed and connected to the multiplexer output. The complete chip is integrated in a 65 nm low power CMOS technology. Capacitive neutralization is used to achieve high gain and good stability for the MOS devices. Also, various differential transmission line topologies are investigated to achieve high performance in terms of loss and area consumption.     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

Differential precoder IC modules for 20-and 40-Gbit/s opticalduobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-μm gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1×10^-9