Evaluation of high-voltage 4H-SiC switching devices

In this paper, the on-state and switching performance of 4H-SiC UMOSFETs, TIGBTs, BJTs, SIThs, and GTOs with voltage ratings from 1 to 10 kV are simulated at different temperatures. Comparison with silicon devices highlights the advantages of SiC technology. SiC BJTs suffer the same problem as Si BJTs, namely the degradation of current gain with increased voltage rating which makes them unsuitable for applications above 4 kV. SiC MOSFETs dominate applications below 4 kV for their attractive conduction performance and advantages such as ease of use. Above 3 kV, SiC MOSFETs are not as attractive as SiC bipolar devices because of their high on-state voltages. In the voltage range simulated, SiC IGBTs, SIThs, and GTOs have comparable current handling ability. Considering the GTOs slow switching speed and drive complexities, IGBTs and SIThs are a better choice in the voltage range 4-10 kV. Calculations based on conduction loss and switching loss indicate that SiC SIThs are superior to IGBTs except in high-temperature and high-frequency applications where IGBTs are better. The need to provide a large gate current during turnoff and turn-off failure caused by gate debiasing, decreases the attractiveness of the SITh     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

1200 V 4H-SiC Bipolar Junction Transistors with A Record β of 70

A common current gain of 70 has been achieved in 4H-SiC bipolar junction transistors (BJTs) at room temperature, which is the highest among those reported. BJTs having an active area of 4 mm × 4 mm exhibit a specific on-resistance of 6.3 mΩ cm² at 25°C, which increases to 17.4 mΩ cm² at 250°C. BV_CEO (the breakdown voltage from collector to emitter with open base) and BV_CBO (the breakdown voltage from collector to base with open emitter) of 1200 V were observed at <5 μA leakage currents at all temperatures up to 250°C. Dynamic characteristics were measured using the IXYS RF/Directed Energy IXDD415 gate driver evaluation board to drive the BJT. A collector current (I _C) rise time at turn-on of 32 ns was measured with a 1.6 A gate current provided to support the collector current of 63 A. An I _C fall time at turn-off of 16 ns was achieved.     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Physical phenomena affecting performance and reliability of 4H-SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300 A/cm². However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H-SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N-P-N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.     

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

Investigation of 4H-SiC MOS capacitors annealed in diluted N2O at different temperatures

Thermally grown oxide on 4H-SiC has been post-annealed in diluted N₂O (10% N₂O in N₂) at different temperatures from 900 to 1100 °C. The quality of the nitrided oxide and the SiO₂/4H-SiC interface was investigated by AC conductance and high frequency C-V measurements based on Al/SiO₂/4H-SiC metal-insulator-semiconductor (MOS) structure. It is found that N₂O annealing at 1000 °C produces the lowest interface state density, though the difference is not so significant when compared to the other samples annealed at 900 and 1100 °C. These results can be explained by the high temperature dynamic decomposition process of N₂O. By fitting the AC conductance data, it is found that higher temperature nitridation increases the capture cross-section of the interface traps.     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.     

High temperature SiC trench gate p-IGBTs

Various design issues pertaining to SiC-based IGBTs are described. A trench gate, p-channel IGBT was considered the most appropriate structure for fabrication in SiC. The fabrication and characterization of high temperature SiC IGBTs with high current levels are presented. Using optimized emitter processing, 6H-SiC p-IGBTs show a higher current capability than 4H-SiC p-IGBTs because of their lower emitter contact resistance and higher MOS channel mobility. Since IGBTs rely on minority carrier injection, the low bulk mobility parallel to the c-axis in 6H-SiC was not found to severely affect the current carrying capability as compared with 4H-SiC IGBTs in the present design. Measured results of these devices are described from room temperature to the 350-400/spl deg/C temperature range. For both polytypes, the current capability was found to be much larger when their MOS gates were fabricated in the 112~0 crystal direction compared with the 1100 crystal direction. The emitter (p-type) contact anneal was also found to significantly affect the performance of SiC IGBTs. 4H-SiC IGBTs showed a -85 V blocking capability (room temperature) and on-current of 100 mA at 350/spl deg/C. 6H-SiC IGBTs were demonstrated with -400 V blocking capability (at 25/spl deg/C) and 2 A at 400/spl deg/C.     

On the assessment of few design proposals for 4H-SiC BJTs

A theoretical design analysis using two-dimensional numerical computer aided design tool (TCAD) is presented for 4H-SiC BJTs. Compared to conventional design, a high p-doped thin layer between the base–emitter region is effective to suppress the surface recombination between the base–emitter region. Using a surface recombination layer (SR layer of 60 nm thickness and acceptor doping of 1.0×10¹⁹ cm⁻³) between base–emitter region, a peak gain of 410 was obtained at 100 A/cm². While a second epitaxy growth run is needed to utilize the advantage of this design, an alternate design with thin high doped (i.e., delta layer design) layer at the base–emitter junction is also interesting from the point of view of improving current gain with reduced on-resistance. A delta layer design thus produces a peak current gain of 300 at 100 A/cm² and on-resistance value of 4 mΩ-cm² at 300 K. Compared to the experimental data of 4H-SiC BJTs, present simulated analysis provides superior performance in terms of current gain.     

Device processing and characterisation of high temperature silicon carbide Schottky diodes

High temperature silicon carbide diodes with nickel silicide Schottky contacts were fabricated by deposition of titanium-nickel metal film on 4H-SiC epitaxial wafer followed by annealing at 550 °C in vacuum. Room temperature boron implantation have been used to form single zone junction termination extension. 4H-SiC epitaxial structures designed to have theoretical parallel-plain breakdown voltages of 1900 and 3600 V have been used for this research. The diodes revealed soft recoverable avalanche breakdown at voltages of 1450 and 3400 V, respectively, which are about 80% and 95% of theoretical values. I-V characteristics of fabricated 4H-SiC Schottky diodes have been measured at temperatures from room temperature up to 400 °C. The diodes revealed unchangeable barrier heights and ideality factors as well as positive coefficients of breakdown voltage.     

High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE

This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 $times$ 1.8 mm (with an active area of 3.24 $hbox{mm}^{2}$) showed a common emitter current gain $beta$ of 42, specific on-resistance $R_{{rm SP}_{rm ON}}$ of 9 $hbox{m}Omegacdothbox{cm}^{2}$, and open-base breakdown voltage $hbox{BV}_{rm CEO}$ of 1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the $hbox{p}^{+}$ regrown layer from the surface of the emitter–base junction. The BJT with $hbox{p}^{+}$ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs with only etched flat-surface JTE.      

High-voltage implanted-emitter 4H-SiC BJTs

Implanted-emitter, epi-base, npn 4H-SiC bipolar junction transistors (BJTs) which show maximum blocking voltage of 500 V and common-emitter current gain (β) of 8 are demonstrated. Compared to the previous results (BV_CEO of 60 V and β of 40), the blocking voltage is greatly improved with reduced current gain due to a decrease of the base transport factor. The samples also show negative temperature coefficient of β, similar to the previous samples, easing device paralleling problems     

Electric properties of (SiC)<Subscript>1 − <Emphasis Type="Italic">x</Emphasis></Subscript>(AlN)<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>/SiC anisotropic heterostructures

The heterostructures of p-(SiC)_{1 − x} (AlN) _x / _n -6H-SiC are synthesized by means of sublimation epitaxy of (SiC)_{1 − x} (AlN) semiconductor solid solutions at 6H-SiC substrates. The results of the investigation of the concentration and temperature dependences on current-voltage characteristics (CVCs) are presented. It is revealed that due to the high potential barriers the forward current is caused by the tunneling and recombination processes of charge carriers via states at the boundary surface.     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Schottky barrier height modification in Au/n-type 6H-SiC structures by PbS interfacial layer

We have prepared the Au/PbS/n-6H-SiC Schottky diodes with interface layer and the reference Au/n-6H-SiC/Ni Schottky diodes without interface layer to realize Schottky barrier height (SBH) modification in the Au/SiC Schottky diodes. The BH reduction has been succeeded by the PbS interlayer to modify the effective BH by influencing the space charge region of the SiC. The PbS thin layer on the SiC was formed by the vacuum evaporation. The SBH values of 0.97 and 0.89 eV for the samples with and without the interfacial PbS layer were obtained from the forward bias current-voltage (I-V) characteristics. X-ray diffraction (XRD) study was carried out to determine the structural formation of the PbS on SiC. The reduction of the BH in the Au/PbS/n-6H-SiC Schottky diodes has been attributed to the fact that the interface states have a net positive interface charge in metal/n-type semiconductor contact, and thus the positive space charge Q_sc in the Au/PbS/n-6H-SiC Schottky diodes becomes smaller than if the interface state charges Q_ss were absent. The experimental carrier concentration value of 4.73 × 10¹⁷ cm⁻³ obtained from the forward and reverse bias capacitance-voltage characteristics for the Au/PbS/n-6H-SiC contacts is lower than the value of 5.52 × 10¹⁷ cm⁻³ obtained for the reference diode, and this is an evidence of the reduction of the BH by the modification of the space charge density of the SiC.     

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

Electrical parameters of a DC sputtered Mo/n-type 6H-SiC Schottky barrier diode

A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (I–V) and capacitance–voltage (C–V) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln I–V plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from C–V measurements was larger than the one obtained from I–V data.