片上变压器隔离门极驱动器的优点

在许多应用中,电气隔离是一项重要的要求,特别是在涉及高功率电路和低功率电路的地方,以及高边和低边接地需要分开的地方。尽管隔离技术已经存在多年了,但已演变以满足新应用的需求,如可再生能源的逆变器、工业自动化、储能以及电动和混合动力汽车的逆变器和正温系数(PTC)加热器,通常使用基于IGBT技术的功率开关来实现这些应用的电...     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.     

A high-performance ZVS full-bridge DC-DC 0-50-V/0-10-A power supplywith phase-shift control

This paper presents a high-performance DC-DC switching mode power supply designed to deliver a regulated 0-50 V/0-10 A output. The proposed power supply is based on a modified version of the zero-voltage switching (ZVS) full-bridge (FB) phase-shift DC-DC converter, which incorporates commutation auxiliary inductors to provide ZVS for the entire load range as well as a commutation aid circuit to clamp the output diode voltage. The control strategy is based on two control loops operating in cascade mode. The inner loop maintains a regulated output current, whereas the external voltage loop regulates the output voltage, independently of load and input-voltage changes. In order to obtain a high-reliability converter, the control circuit has been implemented using just two integrated circuits (ICs). The phase-shift regulator UC3875 IC generates the gate drive signal to the MOSFET's. The control loop regulators are implemented using the TL074 IC. A theoretical analysis was conducted, and experimental results were obtained for a 0-50 V/0-10 A power supply operating at 100 kHz     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

MAGFET based current sensing for power integrated circuit

A new on-chip non-invasive integrated current sensing, compatible with standard CMOS technology, has been developed, using a 1.2 μm BiCMOS ALCATEL technology, to sense the current in the drain side of a power MOSFET. The circuit is based on a split-drain magnetic sensor, implemented on the same chip of an integrated gate driver for a power MOSFET. A CMOS biasing circuit with a differential current output is also developed. The simulation results of the current sensing show a conversion gain of 1.25 mV/mT.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

A monolithic quad line driver for industrial applications

The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V     

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 μm GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.     

大功率IGBT驱动电路的设计

大功率IGBT（绝缘栅双极晶体管）在现代雷达发射机,特别是全固态调制器、高压开关电源中得到广泛应用。其驱动电路要求驱动能力强、保护迅速有效。介绍了互感器触发方式的大功率IGBT驱动电路的设计。该电路具有输出电阻低、电流增益高等优点,并具备快速过流检测和保护功能,解决了IGBT高低电位隔离以及多个IGBT同步驱动问题。实验表明,该驱动电路不仅满足设计要求,而且工作稳定可靠,通用性强,可广泛应用于全固态调制器和高压开关电源。     

40-Gb/s high-power modulator driver IC for lightwave communicationsystems

A monolithic integrated modulator driver with a data decision function for high-speed optical fiber links is presented. The integrated circuit (IC) was manufactured in a 0.2-μm gate length AlGaAs/InGaAs high electron mobility transistor technology with an f_T of 68 GHz. The modulator driver IC features differential configuration and operates up to 40 Gb/s with a clock phase margin of 210° and an output voltage swing of 2.9 V_p-p at each output. The maximum slew rate of the output signal is 200 mV/ps. The power dissipation of the circuit is 1.6 W using a single supply voltage of -5 V     

A monolithic IGBT gate driver for intelligent power modules implemented in 0.8 μm high voltage (50 V) CMOS process

This paper discusses the design and implementation of a monolithic IGBT gate driver for intelligent power modules (IPMs). The objective of this work is to design and implement a monolithic IGBT gate driver IC with efficient protection functions in a high-voltage (50 V) 0.8-μm CMOS process. The gate driver is designed for medium power applications, such as home appliances. It includes low-voltage logic, 5-V logic regulator, analog control circuitry, high-voltage (50 V) high-current output drivers, and protection circuitry.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

集成的B iCMO S DCöD C 开关电源控制器 输出驱动电器的低功耗设计

为使DC／DC开关电源的功率开关管及时地导通或截止,需要设计专用的输出驱动电路,基于整个开关电源系统低功耗的考虑,开关电源可以采用同步整流的拓扑结构。该拓扑结构需要一个电压自举的输出驱动电路,本文首先提出了一种有自举功能的BiCMOS工艺的输出驱动电路,在此基础上,采用电流源和电流沉串联的方式改进了前面提出的输出驱动电路,通过消除CMOS电路的瞬态短路导通现象,不仅降低了该电路模块的功耗,而且起到了保护的作用,经HSPICE模拟表现,开关电源的输入电压Vin为10V控制器内部电压（VL）为5V,开关频率为200kHz时,改进驱动电路的功耗降低了约11．5％,同时避免了瞬态短路导通现象。     

一种高速大电流开关驱动器的设计与实现

设计并实现了一种高速大电流的开关驱动器,可用于驱动PIN开关以及IGBT开关等.开展了系统结构、电路和版图技术研究,并采用亚微米CMOS标准工艺进行设计和制造.通过采用一种带隙基准结构提供偏置的方式使电路兼容TTL和CMOS输入,保证良好的温度特性;通过采用传输门功率驱动电路实现三态控制,解决了高速应用时电容馈通效应问题.详细设计了TTL输入转换电路、基准和偏置电路、三态输出和功率驱动等电路;基于0.6 μm CMOS工艺重点设计了高速驱动器中功率开关版图.该高速大电路开关驱动器产品的传输速度达到了25 ns,驱动电流达500 mA.     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

开关电源全波整流输出结果的对比研究

采用脉宽调制方波作为输入信号,对全桥和半桥驱动型开关电源的输出电压、效率和纹波系数都做了对比分析和研究。并研究了不同频率、占空比以及不同范围的负载电阻对两种工作电路的影响,分析了两种电路各自的优缺点。实验结果表明,半桥驱动型开关电源,在一定程度上限制了驱动电路的最大输出功率,因此在要求大功率输出时还要采用全桥驱动电路。而且全桥工作的效果也要比半桥好,稳定性更强,可为电路的设计提供一个参考。     

用CMOS工艺改善集成开关电容DC-DC变换器的特性

介绍了一种具有改进电路结构和改进工艺的单片集成3.3V/1.2V开关电容DC-DC变换器,其控制脉冲频率和固定导通比分别为10MHz和0.5.为了提高变换器的输出电流,采用CMOS工艺来制造电路中的开关器件和改进的互补型电路结构.使用Hspice电路仿真软件得到的仿真结果表明改进变换器的单个单元电路和互补型电路可使输出电流分别达到12.5mA和26mA,且后者的功率转换效率为73%,输出电压纹波小于1.5%.变换器在日本东京大学的标准Rohm 0.35μm CMOS工艺线上投片试制,测试结果显示,使用CMOS开关的变换器单元电路的输出电流为9.8mA.     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits