Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

In this paper, carrier transport mechanism of MOSFETs with HfLaSiON was analyzed. It was shown that gate current is consisted of Schottky emission, Frenkel-Poole (F-P) emission and Fowler-Nordheim (F-N) tunneling components. Schottky barrier height is calculated to be 0.829 eV from Schottky emission model. Fowler-Nordheim tunneling barrier height was 0.941 eV at high electric field regions and the trap energy level extracted using Frenkel-Poole emission model was 0.907 eV. From the deviation of weak temperature dependence for gate leakage current at low electric field region, TAT mechanism is also considered.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

Microstructure and stress in high-k Hf-Y-O thin films

We investigated the microstructure and the stress of high-k Hf-Y-O thin films deposited by atomic layer deposition (ALD). These hafnium oxide based films with a thickness of 5-60 nm stabilized in crystal structure with yttrium oxide by alternating the Hf- or Y-containing metal precursor during deposition. The microstructure was investigated by XRD and TEM in dependence of substrate and deposition temperature. The film stress was monitored during thermal cycles up to 500 °C using the substrate curvature method on (1 0 0)-Si wafer material with or without 10 nm TiN bottom electrode as well as on fused silica. It was observed that crystallinity and phases are depending on deposition temperature and film thickness. During thermal treatment the films crystallize depending on deposition temperature, yttrium content and substrate material at different temperatures. Crystallization of the films depends strongly on yttrium content. The highest reduction of 720 MPa was observed for films deposited with a Hf:Y cycle ratio of 10:1 where 6.2% of all metal atoms are replaced by yttrium. These Hf-Y-O films also show the highest k-value of 29 and have the smallest thermal expansion coefficient mismatch to TiN electrodes. Therefore we conclude that Hf-Y-O films are candidates for application in next generations of microelectronic MIM-capacitor devices or metal gate transistor technology.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

High-quality high-k HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories

We demonstrate low-trap-density HfON film made by the molecular-atomic deposition (MAD) technique, which is an Ar/N₂ plasma jet assisted physical vapor deposition process. This high-k HfON can be deposited on top of the nearly trap-free MAD-Si₃N₄ to form a single-side crested tunnel barrier. The Al/(HfON-Si₃N₄)/Si capacitor structure with HfON/Si₃N₄ stack as the tunnel barrier demonstrates steeper I-V slope than that of a single layer SiO₂ with the same EOT, and is readily applicable to improve the programming speed and data retention of flash memories.     

Effect of interfacial fluorination on the electrical properties of the inter-poly high-k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al₂O₃ and HfO₂ IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO₂ possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al₂O₃ dielectric is more effective to promote the IPD characteristics than fluorination of the HfO₂ dielectric. For future stack-gate flash memory application, the fluorinated Al₂O₃ IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO₂ IPD due to superior insulating properties.     

X-ray metrology for high-k atomic layer deposited HfxZr1−xO2 films

Hafnium-based dielectrics are the most promising material for SiO₂ replacement in future nodes of CMOS technology. While devices that utilize HfO₂ gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified Hf_xZr_1−xO₂ [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO₂ using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.     

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO₂/HfAlO/SiO₂ triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.