Impact of line-edge roughness on resistance and capacitance of scaled interconnects

The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted.     

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects

We introduce a Nyquist stability analysis of coupled mixed CNT bundle (MCB) for sub-threshold interconnects. In this analysis, the dependence of relative stability of sub-threshold MCBs with specific and probabilistic distribution of CNTs, on the geometry and probability of metallic CNTs, has been obtained. Using the proposed ABCD model and Nyquist stability criterion for sub-threshold MCBs, we show that, by increasing the diameter of each individual CNT and the length of MCB, the sub-threshold MCB interconnect system becomes more stable, while a densely packed MCB reduces the relative stability. Moreover, the crosstalk impact results in the greater stability of sub-threshold MCB system in comparison to a single interconnect. The crosstalk delay of MCB and composite Cu-MWCNT interconnects is also compared at various lengths. This is, so far, the first instance that such an analysis has been presented for coupled sub-threshold MCB interconnects.     

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems

Continuous scaling of conventional hard-wired metal interconnects into deep sub-micrometer region (DSM) has resulted in significant performance degradation in terms of delay, crosstalk noise, higher power dissipation, and decreased tolerance to noise. Besides, communication-centric nature of system-on-chip (SOC) networks requires efficient intra- and inter-chip interconnect technologies. Radio-frequency (RF)/wireless interconnects promise to be the best alternative to metal interconnects as they are compatible with current CMOS-technology, and they also provide higher data rate and bi-directional multi I/O transmissions. This paper evaluates the system bit-error-rate (BER) performance with the application of fault-tolerance capability using linear error-control codes (ECCs) within chip (intra-chip) RF/wireless interconnect systems. It also evaluates the utility of ECCs by considering energy consumed in ECC encoding-decoding vis-à-vis the energy saved due to coding gain by calculating the critical distance (d_cr). The results indicate that for a certain range of received signal-to-noise ratio (SNR), application of ECC improves the BER performance of the RF/wireless interconnect system. It is also shown that d_cr drops to 0.7 mm at 18 GHz.     

Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional I_DDQ testing ineffective. Since natural process variation together with low-V_TH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for I_DDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature I_DDQ testing. We found that the conventional single threshold low temperature I_DDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature ΔI_DDQ test method. The difference between pass and fail current limits was estimated more than 200× for 0.13-μm CMOS technology.     

Drop impact reliability of Sn–1.0Ag–0.5Cu BGA interconnects with different mounting methods

The poor drop-shock resistance of near-eutectic Sn–Ag–Cu (SAC) solder interconnects drives the research and application low-Ag SAC solder alloys, especially for Sn–1.0Ag–0.5Cu (SAC105). In this work, by dynamic four-point bend testing, we investigate the drop impact reliability of SAC105 alloy ball grid array (BGA) interconnects with two different surface mounting methods: near-eutectic solder paste printing and flux dipping. The results indicate that the flux dipping method improves the interconnects failure strain by 44.7% over paste printing. Further mechanism studies show the fine interfacial intermetallic compounds (IMCs) at the printed circuit board side and a reduced Ag content inside solder bulk are the main beneficial factors overcoming other negative factors. The flux dipping SAC105 BGA solder joints possess fine Cu₆Sn₅ IMCs at the interface of solder/Cu pads, which increases the bonding strength between the solder/IMCs and the fracture resistance of the IMC grains themselves. Short soldering time of flux dipping joints above the solder alloy liquidus mitigates the growth of interfacial IMCs in size. In addition, a reduced Ag content in flux dipping joint bulk causes a low hardness and high compliance, thus increasing fracture resistance under higher-strain rate conditions.     

Modeling and analysis of crosstalk induced overshoot/undershoot effects in multilayer graphene nanoribbon interconnects and its impact on gate oxide reliability

Crosstalk induced overshoot/undershoot effects in multilayer graphene nano ribbon interconnects (MLGNRs) are investigated with the help of ABCD parameter matrix approach for intermediate level interconnects at both 11 nm and 8 nm technology node. The worst case crosstalk induced peak overshoot voltage for perfectly specular, doped multilayer zigzag GNR interconnects is comparable to that of copper interconnects. The performance of neutral GNR interconnects is better than that of its doped counterpart with respect to peak crosstalk overshoot. But from the perspective of overall overshoot width and overshoot area contribution, perfectly specular, doped MLGNR interconnects outperform all other alternatives. As far as the effective electric field across the gate oxide is concerned, the doped MLGNR interconnects outperform neutral ones and copper interconnects for all the cases. It is estimated that the doped perfectly specular multilayer GNR interconnects have gate oxide failure rates (AFR) of ~ 240 × and ~ 790 × lesser than copper interconnects for 11 nm and 8 nm technology node respectively. So, from the gate oxide reliability perspective, perfectly specular, doped multilayer zigzag GNR interconnects are great advantageous to copper interconnects for the future integrated circuit technology generations.     

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10 nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using I_leak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced E_OX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.     

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.     

Evolution of Contact Resistance during the Bonding Process of NCA Flip-Chip Interconnections

Non-conductive adhesive (NCA) flip-chip interconnects are emerging as an attractive alternative to lead or lead-free solder interconnects due to their environmental friendliness, lower processing temperatures, and extendability to fine-pitch applications. The electrical connectivity of an NCA interconnect relies solely on the pure mechanical contact between the integrated circuit (IC) bump and the substrate pad; the electrical conductivity of the contact depends on the mechanical contact pressure, which in turns depends to a large extent on the cure shrinkage characteristics of the NCA. Therefore, it is necessary to monitor the evolution of the electrical conductivity which could reflect the impact of cure- and thermal-induced stresses during the curing and cooling process, respectively. In this article, in situ measurement of the development of contact resistance during the bonding process of test chips was developed by using a mechanical tester combined with a four-wire resistance measurement system. A drop of resistance induced by the cure stress during the bonding process is clearly observed. With decreasing bonding temperature, the drop of contact resistance induced by cure shrinkage becomes larger, while the cooling-induced drop of resistance becomes smaller. The evolution of contact resistance agrees well with experimental observations of cure stress build-up. It is found that vitrification transformation during the curing of the adhesive could lead to a large cure stress and result in the reduction of the␣contact resistance. Furthermore, no obvious changes were observed when the applied load was removed at the end of bonding.     

A statistical yield optimization framework for interconnect in double patterning lithography

In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we study the impacts of overlay error on functional and parametric yields of interconnects in 32- and 22-nm technologies. A yield optimization method is applied to derive optimal width and spacing of interconnects for mentioned technologies. Experimental results show that parametric yield loss becomes more problematic in 22-nm technology node compared with the functional yield loss. Moreover, we show that DFM techniques such as wire spreading are necessary to realize the desirable parametric constraints in 22-nm node. Our analysis reveals that overlay electrical impact increases considerably in DPL in the presence of congestion.     

Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Thermoelectric Coolers with Sintered Silver Interconnects

The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm² were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm²) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10^?5 Ω cm² was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.     

Effect of low k dielectrics on electromigration reliability for Cu interconnects

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport dominated by diffusion at the Cu/SiN_x cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)_c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM and found to correlate well with EM lifetime and the (jL)_c product of low-k interconnects.     

Electro-thermal resistance of GaAs interconnects

This paper describes the effect of steady-state heating on the electrical and thermal resistance of interconnects on GaAs. Examined is a typical dual-layer metal interconnect system, common to GaAs processing. The interconnect system is considered in three parts, the interconnect metals, the Si₃N₄ dielectric surrounding the metal, and the Al _x Ga_1−xAs epitaxial substrate. Using a mean-dering line as a test structure, measurements show how the direct current (DC) resistance increases with both temperature and dissipated power. Thermal resistors are proposed to account for self-heating and thermal coupling.     

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48 h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1 Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d · jL)_crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.     

Electromigration in electroplated Cu(Ag) alloy thin films investigated by means of single damascene Blech structures

Electromigration failure of copper interconnects in microelectronics evokes a need for materials with improved resistance against electromigration effects. Copper–silver alloy thin films are a promising material for the next generation of interconnects and were investigated with respect to their electromigration resistance. The investigations were done by atom drift experiments by means of Blech structures fabricated in single damascene technology with two different Ta-based liner systems. Electromigration induced atom drift could be demonstrated. The resistance against electromigration of Cu(Ag) films appears to be slightly higher than for pure Cu films. However, significant experimental errors are still present. Additionally, de-alloying effects were observed.     

Stabilizing effects for the supercritical GaAs n+nn+-transferred electron amplifier

In this paper effects of importance for the stabilization of supercritical n⁺nn⁺ GaAs transferred electron devices are considered. By small-signal impedance calculations and measurements it is shown that doping- as well as temperature gradients of correct polarity reduce the device negative resistance and enhance stability. It is also found that an increasing doping density reduces the negative resistance. Finally it is demonstrated that relaxation effects have a profound influence on the impedance, and that such effects have to be included in a small-signal analysis in order to give reasonable agreement with measurements.     

Interface reliability and lifetime prediction of heavy aluminum wire bonds

In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔT_j) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔT_j and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.