Reduction in Reflections and Ground Bounce for Signal Line Over Slotted Power Plane Using Differential Coupled Microstrip Lines

This paper investigates the noise reduction in the slot-induced ground bounce noise by using differential signaling. An efficient 2-D finite-difference time-domain method together with equivalent circuits for both the differential line and the slot is established and simulations are performed for a three-layer structure to characterize the ground bounce coupling. A simple model is then proposed to understand how the differential coupled microstrip lines can help reduce ground bounce. Different factors which affect noise reduction are investigated, such as the coupling coefficient, rising time, skew of differential signaling, and structure asymmetry in slotline. An experimental setup is devised to demonstrate the noise coupling between signal lines due to the slot-induced ground bounce and significant noise reduction by employing differential signaling. A favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.      

Ground bounce in digital VLSI circuits

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.     

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.     

高速PCB电源完整性研究

一块成功的高速印刷电路板(PCB),需要做到信号完整性和电源完整性,首先必须降低地弹.为了滤除地弹骚扰,推荐在电源/地平面对上,安放去耦电容。     

Forming damped LRC parasitic circuits in simultaneously switchedCMOS output buffers

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-μm CMOS test chip have demonstrated that these new buffers generate 2.5× less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current     

Design of output buffer with low switching noise and load adaptability

A new CMOS output buffer with low switching noise and load adaptability is presented in this paper. By designing an innovative combination structure of two driving stages, the buffer can reduce switching noise and output ringing with no penalty on signal transmission speed. Furthermore, the buffer can automatically adjust the total driving capability in response to variation of loading condition, the load adaptive method is simple and effective without the necessity for a feedback circuit. The proposed buffer has been designed in a TSMC 90 nm CMOS process. Simulation results demonstrate that the proposed buffer achieves 4.1–53.5% improvements in ground bounce and 2.9–15.2% reductions in output ringing compared with those of the AC/DC buffer. Meanwhile, it reduces ground bounce by 6.5–17.6% and output ringing by 3.8–10.9% relative to the CSR buffer.     

分形粗糙面上方目标电磁散射特性的研究

利用分形函数来模拟海地粗糙表面，在考虑到粗糙面的粗糙度，入射波极化方式以及粗糙面的动态和静态等因素对电磁散射特性影响的情况下，运用克希霍夫近拟条件，对粗糙面上方平板目标电磁散射的物理机制进行了分析和研究。理论分析和数值结果表明，本文所述方法物理图象清晰，是一种有效分析实际粗糙面与目标相互作用的方法。     

A canonical problem in electromagnetic backscattering from buildings

In this paper, a geometric and electromagnetic model of a typical element of urban structure is presented, in order to analytically evaluate in closed form its electromagnetic return to an active microwave sensor. This model can be used to understand what information on geometric and dielectric properties of a building can be extracted from microwave remote sensing data. The geometrical model consists of a rectangular parallelepiped whose vertical walls form a generic angle with respect to the sensor line of flight. The parallelepiped is placed on a rough surface. The radar return from such a structure can be decomposed into single-scattering contributions from the (rough) ground, the building roof (a plane surface in our model), and vertical walls and multiple scattering contributions from dihedral structures formed by vertical walls and ground. In our model, single-scattering contributions are evaluated by using either physical optics (PO) or geometrical optics (GO), depending on surface roughness. In order to account for multiple scattering between buildings and terrain, we use GO to evaluate the field reflected by the smooth wall toward the ground (first bounce) or the sensor (second or third bounce) and GO or PO (according to ground surface roughness) to evaluate the field scattered by the ground toward the wall (first or second bounce) or the sensor (second bounce). Finally, the above model is used to analyze the field backscattered from a building as a function of the main scene parameters; in particular, the angle between vertical walls and sensor line of night and the dependence on the look angle are analyzed.     

A theoretical investigation of the resonance damping performance of magnetic material coating in power/ground plane structures

Power bus structure, consisting of two parallel solid power and ground planes separated by an insulator, behaves as a cavity resonator at high frequencies. Noise on the power bus, due to a sudden change in the current drawn by an active component, can appear as an undesired spatial fluctuation in the voltage between power and ground, especially at resonant frequencies of the resultant cavity, which may lead to problems in signal integrity, excessive delays, false switching, and radiated emission. These resonances can be suppressed by introducing high-frequency loss into the structure. This paper investigates a simple method to reduce self-/transfer impedance of power/ground planes for mitigating power/ground bounce in high-speed printed circuit board design by adding a thin layer of magnetic material coating to the inside-facing surfaces of copper power and ground plates to increase their effective high-frequency surface impedance. The increased surface impedance will increase the attenuation constant of the propagating wave inside the cavity that benefits reduction of cavity's quality factor (Q factor). The simulation results obtained from a modified cavity resonator model show that increasing surface impedance can dramatically reduce self- and transfer impedances at board resonant frequencies.     

基于核ICA的探地雷达地杂波抑制

地雷及未爆武器给许多国家带来了巨大的经济和社会问题。近年来超宽带探地雷达被广泛用于浅层埋藏的塑性地雷的检测,其中滤除雷达回波信号中的地杂波是完成目标检测、成像与识别的关键。文中通过利用核ICA算法进行研究,给出了一种可以针对多目标数据区域且自动选取独立分量的探地雷达地杂波抑制方法,基于实测数据的实验结果表明了该方法的有效性。     

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, power-gating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V _th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.     

CMOS电路同步开关噪声的分析和仿真

目前,集成电路正向着高速集成度方向发展,但受到封装如DIP、TSOP、BGA等上寄生电感的作用,同步开关噪声影响越来越大。本文对一个简化的同步开关噪声电路模型进行了理论分析,从而得出通过调整开关上升时间等方法,可以有效降低地弹噪声,降低幅度可达到80％以上。     

Composite effects of reflections and ground bounce for signal line through a split power plane

The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in signal return path and ground bounce between power and ground planes. A new equivalent circuit model is proposed and simulations are performed for multilayer structures to characterize these composite effects. An experimental setup is devised to demonstrate significant coupling between signal lines due to the slot-induced ground bounce. Favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.     

A novel signal processing technique for clutter reduction in GPR measurements of small, shallow land mines

A signal processing technique is developed to reduce clutter due to ground bounce in ground penetrating radar (GPR) measurements. This technique is especially useful when a GPR is used to detect subsurface antipersonnel mines. The GPR clutter is modeled using a simple parametric model. Buried mine and clutter contributions are separated through a pair of coupled iterative procedures. The algorithm outperforms existing clutter reduction approaches and also yields target features that are useful for detection and identification of these mines. The proposed technique effectively reduces clutter resulting in a significant decrease in false alarm rates.     

Study of the ground bounce caused by power plane resonances

We describe Delta-I noise caused by power plane resonances in multilayer boards. First, we study the effect of power plane resonances on the ground bounce of the system by performing finite-difference time-domain (FDTD) simulations. We simulate the voltage fluctuations at one point of the printed circuit board (PCB) due to a current surge between the power planes in a different point. Next, two methods to prevent this ground bounce effect are investigated. The first method consists of adding lumped capacitances to the design. The effect of one large capacitor is compared to the effect of adding a “wall” of smaller capacitors. A second approach is to isolate the chips by etching a slot around the sensitive integrated circuits (ICs) and connecting both sides by a small inductor. Both methods provide excellent protection against power plane resonances     

几何模型约束的SAR图像建筑物提取

利用高分辨率SAR图像进行建筑物提取的常规方法是首先利用二次散射特征线确定建筑物边界, 然后利用叠掩、阴影等散射特征来提取建筑物高度.当建筑物目标走向与星载SAR方位向夹角较大时, 其二次散射特征不明显, 常规重建方法不能取得理想结果.针对这类建筑物目标, 在分析SAR图像上的散射特征为平行四边形条带的基础上, 提出一种基于几何模型约束的建筑物自动提取与三维重建方法.将该方法应用于TerraSAR-X聚束模式图像, 并对提取结果进行了分析和评价, 表明该方法能够有效提取建筑物目标及其三维信息.     

Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology

In the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage V_dd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10^?14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd.     

系统级封装新型埋入式电源滤波结构的研究

在高密度小尺寸的系统级封装(SiP)中,对供电系统的完整性要求越来越高,多芯片共用一个电源网路所产生的电压抖动除了会影响到芯片的正常工作,还会通过供电网路干扰到临近电路和其他敏感电路,导致芯片误动作,以及信号完整性和其他电磁干扰问题.这种电压抖动所占频带相当宽,几百MHz到几个GHz的中频电源噪声普通方法很难去除.结合埋入式电容和电源分割方法的特点,提出一种新型高性能埋入式电源低通滤波结构直接替代电源/地平面.研究表明,在0.65～4GHz的频带内隔离深度可达-40～75 dB,电源阻抗均在0.25ohm以下,实现了宽频高隔离度的高性能滤波作用.分别用电磁场和广义传输线两种仿真器模拟,高频等效电路模型分析这种低通滤波器的工作原理以及结构对隔离性能的影响,并进行了实验验证.     

Estimation of ground bounce effects on CMOS circuits

Ground bounce estimation is important to determine the impact of simultaneous switching of input/output (I/O) drivers and clock drivers on the performance of application-specific integrated circuits (ASIC's). In this paper, we develop models to estimate the peak and damped resonance noise of the ground and power bounce. These models are developed for both long and short channel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simple and suitable for hand calculation     

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.