汽车电子芯片EMC测试标准研究

在汽车电子产品所采用的电磁兼容测试标准的基础上,以功率驱动芯片为例,提出了汽车电子芯片级电磁兼容测试的必要性,并重点介绍了集成电路电磁发射测试标准IEC61967和集成电路电磁抗扰度测试标准IEC62132。     

EMC awareness for multi chip modules

As more and more complex functions are realized in modern IC designs, there is also an increasing need to design the IC in order to satisfy the Electromagnetic Compatibility (EMC) requirements. Without a proper design, the high operating frequencies of modern integrated circuits often result in high emissions. Due to the cost pressure on mobile phones and other portable devices, shielding on the PCB is avoided and as a result, the electromagnetic emission of integrated circuits must be reduced. This article provides an overview of design methodologies for achieving EMC of devices implemented in systems in package (SiP) technologies. It exhibits the importance to imply EMC issues in the early design phase to reduce electromagnetic emissions.     

集成电路电磁兼容标准概述

随着集成电路新技术与应用的结合，增加了电磁兼容(EMC)符合性的复杂程度，对ICEMC性能的表征受到越来越多的关注。由此推动了对标准化测量规程的需求，使不同器件有一致的评价和比较。对标准化的需求进行了讨论，介绍了IECTC47／SC47A第9工作组在IC发射与抗扰度EMC试验方法标准化方面的工作进展情况。并探讨了ICEMC的发展趋势。     

Power bus signal integrity improvement and EMI mitigation on multilayer high-speed digital PCBs with embedded capacitance

The continuous technology trend in the telecommunication market toward higher operating frequencies and high processing performances will give rise to new sophisticated chip sets, processors, and RF transceivers which will demand new feature to the PCB designs. As the complexity of the integrated circuits increases, signal integrity (SI) and electromagnetic compatibility (EMC) become key elements in the board design process. This paper analyzes the beneficial effects that a thin dielectric material between a pair of power and ground layers (embedded capacitance) has both in reducing power bus resonance amplitudes (SI approach) and radiated emissions (EMC approach) as well. Scattering parameter measurements carried out on the power bus of two production boards are presented and correlated with the electric field strength measurements conducted on the same boards in a semianechoic chamber.     

Assessment of digital integrated circuit electromagnetic emissionbased on radiated power evaluation

This paper deals with the assessment of digital integrated circuit (IC) electromagnetic emission (EME), and concentrates on the specific aspect of EME of long external wiring, driven by IC input-output pins. In particular, the contribution of single IC pins is investigated by analyzing the structure composed of an IC output driver connected via a microstrip line to a receiver. A transmission-line model is used, and an approach based on the concept of radiated power is applied to the characterization of single-pin IC EME in terms of external-wiring radiation effects. By the analysis of typical driver-wiring configurations, it is shown that the spectrum of the driver output current is the quantity of interest, and that the use of wiring with smaller characteristic impedance leads to larger radiated power. The use of a specific test setup (IEC 61967-4-150-Ω direct coupling method) for the experimental assessment of single pin IC emissions is also considered. Frequency-dependent setup effects are experimentally ascertained via a scattering parameter characterization, and definition of suitable circuit functions. An estimate of the degree of correlation between voltage measurements foreseen by the test procedure and the total power radiated by the loading network of an IC driver is derived     

An overview of standards in electromagnetic compatibility for integrated circuits

The characterization of the electromagnetic compatibility (EMC) performance of integrated circuits (ICs) is receiving increasing focus as new applications and technology trends combine to raise the complexity of EMC compliance. The increased focus is driving the need for standardized measurement procedures to enable consistent evaluation and comparison of different devices. This paper discusses the need for standardization, describes the work in process by IEC TC47/SC47A Working Group 9 to standardize emissions and immunity EMC test methods for ICs, and examines trends in IC EMC.     

Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory

Due to the complexity of IC, electromagnetic immunity plays a critical role towards evaluating the EMC performance to avoid the high cost of redesign. This paper focuses on the Direct Power Injection (DPI) immunity of processor chips with different external double data rate3 (DDR3) synchronous dynamic random access memory (SDRAM) in consumer electronics. To complete the DPI test, a test board complying with the standard IEC62132-4 and a dedicated test code have been designed. The effect of DC power injection interference on same DDR model but different DDR pins and the same DDR pin but different DDR models were analysed, the results can be used to locate the system-level EMC issues and optimize the design.     

Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits

This paper presents a comparative study of susceptibility reduction techniques for electromagnetic interference (EMI) in digital integrated circuits (ICs). Both direct power injection (DPI) and very-fast transmission-line pulsing (VF-TLP) methods are used to inject interference into the substrate of a single test chip. This IC is built around six functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low emission design rules. The ranking of three of these cores in terms of electromagnetic immunity is then compared with the one of their radiated emission, thanks to near-field scanning (NFS) measurements. This leads to the establishing of design guidelines for low EMI in digital ICs.     

基于横电磁波小室的IC辐射发射测试方法研究

集成电路(IC)的发展呈现出小型化和集成化的趋势,使得IC电磁辐射越来越强,准确测试出IC电磁辐射对于集成电路电磁兼容设计有重要意义。横电磁波(TEM)小室法是目前最常用的IC辐射测试方法,它使用方形测试板,测试四个角度(0°, 90°, 270°, 360°)的IC辐射值,然而IC电磁辐射具有角度效应,仅用四个角度无法准确测试出IC最大电磁辐射水平。文中基于TEM小室全波仿真模型,使用单根微带线,验证了角度对于IC辐射的影响。设计了基于STM32芯片的圆形测试板和方形测试板,利用TEM小室测试了不同角度、不同模式下的STM32芯片电磁辐射,测量结果证实了不同模式下圆形测试板的测试结果都要大于方形测试板,最大偏差达到16 d Bm,因此圆形测试板更能准确测出芯片的最大电磁辐射水平。     

Characterization of the Evolution of IC Emissions After Accelerated Aging

With the evolving technological development of integrated circuits, ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution of EMC over time is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emissions. Different types of standard applicative and accelerated life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emissions are measured before and after these tests, showing variations in EMC performance. Comparisons between each type of aging procedure show that the emission level of the circuit under test is differently affected.      

弧焊设备电磁兼容性要求的新国标即将出台

有关弧焊设备电磁兼容性要求的新国标已参照最新版IEC60974-10：2007首次制定,比较了IEC60974-10：2007与IEC60974-10：2004两者在弧焊电源电磁发射限值、抗扰度要求和试验条件等方面的差异和要求,并分析其对弧焊电源电磁兼容测试的影响,以指导弧焊设备生产厂家应对电磁兼容强制要求。     

毫米波相控阵封装天线电磁兼容仿真分析与设计

提出了一种毫米波相控阵封装天线的建模方法,通过商业仿真软件搭建了相控阵封装天线集数字、模拟和射频于一体的系统级仿真模型。基于此模型,分析了毫米波相控阵封装天线典型电磁兼容问题机理。此外,提出了相控阵封装天线电磁兼容设计的基本原则。原理样机试验和装机试飞验证了所提出的电磁兼容建模、仿真、分析和设计方法的有效性与正确性。     

非接触式IC卡射频前端电路设计

给出了一种基于 ISO/IEC1 44 4 3 -2标准的非接触式 IC卡射频前端电路设计方案 ,详细叙述了典型模块的设计思路。本设计采用 0 .8μm CMOS工艺流水 ,设计工作频率为 1 3 .5 6MHz,数据传输速率为 1 0 6kbps。文中给出了 Hspice模拟和相应的芯片测试结果 ,验证了设计     

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.     

高速混合电路的EMC设计

高速混合电路在很多重要领域都有应用.高速混合电路中的主要噪声源和EMC设计方法都有新的重要特点,传统的EMC设计方法已难以满足实际需要.结合IC技术、PCB技术和EMC技术的新进展和发展趋势,讨论了高速混合电路中的主要噪声源(包括△I噪声、时钟噪声、电源噪声、ESD噪声等),研究了高速混合电路的若干值得重视与进一步研究的EMC设计方法(涉及IC封装技术、PCB技术、EMC预测技术、EDA技术、时钟展频技术、ESD防护技术等).对高速混合电路的EMC设计方法的研究与应用具有指导作用.     

Issues in electromagnetic compatibility of integrated circuits: emission and susceptibility

This paper is focused on the electromagnetic compatibility (EMC) of integrated circuits. The introduction gives general keyword definitions and principles for emission and susceptibility. The second part deals with the evolution of integrated circuit design and technology with its consequences on EMC. The third part describes the mechanisms for generating parasitic noise within integrated circuits and the role of the package and on-chip supply network. Next, the standardized measurement methods are described for both parasitic emission characterization (conducted and radiated) and immunity from 1 MHz to 1 GHz. Issues and proposals up to 18 GHz are discussed. The advances in modeling of emission are also addressed, as well as the issues in immunity prediction.     

使用发射信道模型降低液晶显示屏电磁干扰

本文介绍一种发射通道模型来仿真液晶显示屏所产生的电磁干扰噪声。通道模型包含基于IEC61967-2标准(横电磁波传输室的辐射发射)的封装、印刷电路板以及辐射柔性印刷电路板等模型来仿真电磁发射能量。最后,本文所用的仿真平台已经验证带有不同时序控制驱动器的真实37"液晶显示屏,而实验结果显示降低电磁干扰的效果极佳。配合所提出的发射通道模型,我们能够很容易的设计低发射驱动器,避免因电磁干扰问题所导致的成本增加。     

Characterization and modeling of parasitic emission in deep submicron CMOS

This paper presents a study of the parasitic emissions of a 0.18-/spl mu/m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV