集成电路电磁兼容标准概述

随着集成电路新技术与应用的结合，增加了电磁兼容(EMC)符合性的复杂程度，对ICEMC性能的表征受到越来越多的关注。由此推动了对标准化测量规程的需求，使不同器件有一致的评价和比较。对标准化的需求进行了讨论，介绍了IECTC47／SC47A第9工作组在IC发射与抗扰度EMC试验方法标准化方面的工作进展情况。并探讨了ICEMC的发展趋势。     

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.      

Numerical tools for simulation of radiated emission testing and its application in uncertainty studies

Radiated emission measurements are used to test whether electronic products comply with certain EMC emission requirements. Stimulated by the need to reduce uncertainties, the radiated emission measurement is subject to modification by the EMC standardization body CISPR. Simulation tools are very useful in supporting such modifications. In this paper, we evaluate the use of numerical tools based on the method of moments (MoM) for the simulation of radiated emission testing. We also examine whether such a tool is capable for performing parameter variation studies. For this parameter study, we focus on height and distance variations of the equipment under test (EUT). The results of the parameter study are validated by measurements. The influence of EUT height or distance variations is predicted very well by numerical tools.     

CBGA、CCGA植球植柱焊接返工可靠性研究

多功能、高性能、高可靠及小型化、轻量化是集成电路发展的趋势。以航空航天为代表的高可靠应用中,CBGA和CCGA形式的封装需求在快速增长。CLGA外壳/基板植球或植柱及二次组装之后的使用过程中,常出现焊接不良或其他损伤而导致电路失效,因此需要进行植球植柱焊接返工。在返工过程中,除对焊接外观、焊接层孔隙等进行控制,研究返工过程对植球植柱焊盘镀层的影响也是保证焊接可靠性的重要工作。一次返工后焊盘表面镀金层已不存在,镀镍层也存在被熔蚀等问题,这都对返工工艺及返工后的电路可靠性提出了挑战。文章主要研究返工中镀镍层熔蚀变化趋势以及随返工次数增加焊球/焊柱拉脱强度和剪切强度的变化趋势,并分析返工后电路植球植柱的可靠性。     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

The semiconductor roadmap for power management in the newmillennium

Power management holds the key to over $400 billion annual savings in electrical energy and is relieving critical bottlenecks in the Internet backbone, Internet appliances and portable electronics. The latest analog integrated circuits and power semiconductors are enabling these improvements. This paper focuses on these leading-edge devices, used in conjunction with innovative architectures. The authors examine future trends in silicon-based power transistors and diodes and discuss how the changing requirements of end users are driving new analog ICs, as well as different power management architectures. Trends in architecture for DC-DC power conversion and motion control set the stage for improvements needed and planned in the power management products over the next several years. They examine various technologies for analog ICs and their interface with the digital world. They also compare the pros and cons of different techniques and levels of “power-plus-control integration”. The discussion on power MOSFETs (including IGBTs) focuses on performance and technology trends in DC-DC power conversion and motion control. State-of-the-art and future device topologies are presented. The future of diodes is also discussed. DC-DC conversion and motion control is the context. State of the art and future device topologies are presented. Less than 25% of all the world's electricity is efficiently managed. Roadmaps must focus not only on making existing applications more efficient and cost-effective, but also on enabling the new applications that can address the remaining 75%     

High-speed optical transmission systems using advanced monolithicIC technologies

The authors discuss the design and performance of monolithic ICs for multigigabit lightwave transmission systems including direct detection and coherent detection. The required function and performance of a lightwave transmitter and receiver are discussed. The fabricated ICs and their application to the transmission system are shown in a direct system. Microwave monolithic ICs for lightwave heterodyne detection and an interconnection technique are introduced. Future trends of ICs are discussed     

ICEM modelling of microcontroller current activity

Better prediction of electromagnetic compatibility (EMC) for components is becoming a topical demand due to technology improvements. It is requested by integrated circuit (IC) manufacturers as well as by equipment integrators. The French UTE standardisation group has proposed an EMC modelling methodology for ICs, called integrated circuit electromagnetic model (ICEM). This proposal improves and extends the IBIS standard towards conducted emission prediction (and later radiated emission) by providing additional information modelling the power network and the dynamic current activity of an IC, thus allowing the chip manufacturer to justify the package used as well as the number of power supply pins, and the equipment manufacturer to tune power supply and decoupling networks.After a brief introduction to the ICEM model and the associated methods, this article shows a way of obtaining dynamic current activity models by measuring the current consumed on the IC power supply pins. The use of ICEM for the optimisation of decoupling networks, the evaluation of power supply noise and the tuning of the surface of power and ground planes is presented for the first time with subsequent results.     

Performance-Optimized Design for Parametric Reliability

Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations (Bowman et al., IEEE J Solid State Circuits 37:183–190, 2002), making it a significant problem for design and manufacture of DSM ICs. Adaptive design techniques are fast evolving as a potential solution to this problem. Such techniques facilitate reconfiguration of an IC to enable its operation across process corners, thus ensuring parametric reliability in such ICs, and also improving manufacturing yield. In this paper, adaptive design techniques with a focus on timing of ICs, i.e., performance-optimized adaptive design, are explored. The focus of such performance-optimized adaptive design techniques is to ensure that adaptation does not cause an IC to violate timing specifications, thus giving priority to performance, which remains one of the most important parameters of an IC.     

低压大电流型永磁同步电动机驱动电路设计

在电动汽车等应用中,低电压和大电流的特点使得永磁同步电动机的驱动电路不同于一般通用驱动器。基于DSP TMS320F2812以及IR2110等核心芯片,在系统整体方案、功率电路、抗电磁干扰以及二次隔离电源等方面需要针对该特点进行了设计。在轴角变换的基础上采用空间矢量SFWM实现电机的控制。同时采用负偏压悬浮驱动等电路结构形式,简化了二次隔离电源的设计     

平板显示器驱动芯片高低电压转换电路

LCD、PDP、VFD等各类平板显示器已越来越受到人们关注与喜爱,但大多数平板显示器需要专用的功率驱动芯片来驱动其发光显示,各类专用功率驱动芯片又离不开高低电压转换电路,高低电压转换电路性能的好坏直接影响到驱动芯片的稳定性和功耗等。通过比较平板显示器驱动芯片的几种典型高低压转换电路,设计出一种带有电流源的CMOS型高低压转换电路,它具有最佳的性能指标,该电路不但可以为平板显示器驱动芯片使用,还可以作为其他各类驱动芯片的高低压转换模块使用,最后给出一种具体的平板显示驱动芯片高压CMOS器件结构。     

Trends in CAD of analog ICs

This article presents views on the current trends in the field of computer-aided design (CAD) of analog integrated circuits (ICs), as gathered from a broad survey. The survey was conducted across various academic institutions and semiconductor industries, as well as government research funding agencies. The survey requested in-depth responses and the results were qualitative in nature, therefore, no numerical tabulation was possible. The future directions for the analog CAD field as presented in the survey indicate a need for increased activity and developments. The article gives an overview of analog circuit design and then summarizes the survey results, which are fairly detailed and cover various aspects of the analog circuit design automation process     

Adhesion improvement of Cu-based substrate and epoxy molding compound interface by hierarchical structure preparation

For microelectronic industry, Cu-based substrate and epoxy molding compound (EMC) interface is inherently weak and most likely to delaminate, well-known as a major threat for integrated circuits (ICs) reliability. In this paper, hierarchical whisker-like oxide/Cu cone structure was for the first time to be fabricated by combining electroless plating with heat treatment methods to enhance the interface adhesion between Cu-based substrate and EMC. The surface morphology was characterized by scanning electron microscope (SEM). Result shows that the hierarchical whisker-like oxide/Cu cone film is fine, dense and uniform; Single Cu cone structure is about 3–5 μm in height and 1 μm in root diameter; a layer of whisker-like oxide grows perpendicularly to circular surface of Cu cone, with length ranging from tens to hundreds of nanometers. Adhesion strength between the as-prepared substrates and EMC were measured by button shear test. With consideration of oxidation caused by practical processes (e.g. wire bonding), the interface of EMC and porous oxide formed at 260 °C for 5 min was taken as standard sample, representative of practical interface. To further study the effect of whisker-like oxide and Cu cone solely on adhesion performance, whisker-like oxide, porous oxide/Cu cone were investigated as well. Button shear test results reveal that interfacial adhesion strength of EMC and whisker-like oxide, porous oxide/Cu cone, hierarchical whisker-like oxide/Cu cone are 85%, 110% and 162% higher than that of standard interface. Moreover, the mechanism for adhesion improvement was discussed by facture surface observation, failure path assumption and force–displacement curve analysis. Results show that interface of EMC and hierarchical whisker-like oxide/Cu cone exhibits brittle/ductile property with about 3–5 μm thick EMC left on the fracture surface, indicating cohesive failure caused by remarkable mechanical interlocking effect.     

Understanding IC lithography

Factors such as minimum resolution overlay tolerances and maximum topography are key elements of IC fabrication. Circuit designers must understand the techniques lithographers use in manufacturing ICs. An overview of the resist work performed at SEMATECH, including resist characterization, process control, and modeling, and a look at future lithography trends are presented. Swing curve, exposure/focus latitude, contrast, reflective notching, development rate, and plasma and thermal resistance measurement procedures for performing resist evaluations are discussed     

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.     

高速混合电路的EMC设计

高速混合电路在很多重要领域都有应用.高速混合电路中的主要噪声源和EMC设计方法都有新的重要特点,传统的EMC设计方法已难以满足实际需要.结合IC技术、PCB技术和EMC技术的新进展和发展趋势,讨论了高速混合电路中的主要噪声源(包括△I噪声、时钟噪声、电源噪声、ESD噪声等),研究了高速混合电路的若干值得重视与进一步研究的EMC设计方法(涉及IC封装技术、PCB技术、EMC预测技术、EDA技术、时钟展频技术、ESD防护技术等).对高速混合电路的EMC设计方法的研究与应用具有指导作用.     

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.     

GaAs ICs for high-speed signal processing

A complete family of small-scale integration (SSI) and middle-scale integration (MSI) analog and digital GaAs ICs for real-time signal processing is reported. These circuits have been used on several microstrip PC board applications with clock frequencies ranging from 500 MHz to 1 GHz. Detailed circuit performances and future trends are presented and discussed     

“Digital television”: will the chips be available?

Siemens engineer R.Luder looks at the trends in feature size and complex geometry arrangements in todays ICs. The intention is to highlight what is needed, in Siemens view, for the future Digital TV era.     

Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling of state-of-the-art work in power reduction techniques, and also in the newly emerging area of statistical optimization applied to very large scale integration (VLSI) ICs. The lack of CAD techniques to perform multiobjective function optimization (specifically parametric yield under correlated performance metrics) is a major limitation of current CAD research. In addition, with design trends pushing towards architectures based on aggressive adaptivity and voltage scaling, CAD researchers and engineers will need to refocus efforts on enabling this type of complex design