A system architecture solution for unreliable nanoelectronic devices

The shrinking of electronic devices will inevitably introduce a growing number of defects and even make these devices more sensitive to external influences. It is, therefore, likely that the emerging nanometer-scale devices will eventually suffer from more errors than classical silicon devices in large scale integrated circuits. In order to make systems based on nanometer-scale devices reliable, the design of fault-tolerant architectures will be necessary. Initiated by von Neumann, the NAND multiplexing technique, based on a massive duplication of imperfect devices and randomized imperfect interconnects, had been studied in the past using an extreme high degree of redundancy. In this paper, this NAND multiplexing is extended to a rather low degree of redundancy, and the stochastic Markov nature in the heart of the system is discovered and studied, leading to a comprehensive fault-tolerant theory. A system architecture based on NAND multiplexing is investigated by studying the problem of the random background charges in single electron tunneling (SET) circuits. It might be a system solution for an ultra large integration of highly unreliable nanometer-scale devices.     

Silicon nanoelectronic devices with delta-doped layers

Electronic devices grown by molecular beam epitaxy on a nanometer scale are presented. The use of a vertical device design in combination with delta-doping layers increases the performance of these devices. The vertical design offers the possibility of three dimensional device integration and allows the scaling of MOS field effect transistors down to its physical limits. The excellent crystal quality and doping profile is demonstrated by the very good performance of the grown devices.     

The fabrication and application of Ni-DNA nanowire-based nanoelectronic devices

DNA is a self-assembled, double stranded natural molecule that can chelate and align nickel ions between its base pairs. The fabrication of a DNA-guided nickel ion chain (Ni-DNA) device was successful, as indicated by the conducting currents exhibiting a Ni ion redox reaction-driven negative differential resistance effect, a property unique to mem-elements (1). The redox state of nickel ions in the Ni-DNA device is programmable by applying an external bias with different polarities and writing times (2). The multiple states of Ni-DNA-based memristive and memcapacitive systems were characterized (3). As such, the development of Ni-DNA nanowire device-based circuits in the near future is proposed.

     

Carbon nanotube nanoelectronic devices compatible with transmission electron microscopy

We report on a novel method to fabricate carbon nanotube (CNT) nanoelectronic devices on silicon nitride membrane grids that are compatible with high resolution transmission electron microscopy (HRTEM). Resist-based electron beam lithography is used to fabricate electrodes on 50 nm thin silicon nitride membranes and focused-ion-beam milling is used to cut out a 200 nm gap across a gold electrode to produce the viewing window for HRTEM. Spin-coating and AC electrophoresis are used as methods to deposit small bundles of carbon nanotubes across the electrodes. We demonstrate the viability of this approach by performing both electrical measurements and HRTEM imaging of solution-processed CNTs in a device.     

Nanoscale resistive switching devices for memory and computing applications

With the slowing down of the Moore’s law and fundamental limitations due to the von-Neumann bottleneck, continued improvements in computing hardware performance become increasingly more challenging. Resistive switching (RS) devices are being extensively studied as promising candidates for next generation memory and computing applications due to their fast switching speed, excellent endurance and retention, and scaling and three-dimensional (3D) stacking capability. In particular, RS devices offer the potential to natively emulate the functions and structures of synapses and neurons, allowing them to efficiently implement neural networks (NNs) and other in-memory computing systems for data intensive applications such as machine learning tasks. In this review, we will examine the mechanisms of RS effects and discuss recent progresses in the application of RS devices for memory, deep learning accelerator, and more faithful brain-inspired computing tasks. Challenges and possible solutions at the device, algorithm, and system levels will also be discussed.

     

State-of-the-art technologies and devices for high-voltage integrated circuits

The current status of high-voltage power semiconductor devices and technologies for high-voltage integrated circuits is reviewed and the new trends in this field are discussed. The paper focuses on the concepts of the novel reduced surface field and state-of-the-art silicon technologies such as high-voltage silicon on insulator, which are expected to play an increasingly important role in power system on-chip manufacturing. Lateral devices such as LDMOSFETs, superjunctions and lateral insulated gate bipolar transistors are discussed. The paper also touches on emerging technologies such as unified MEMS-IC for enhanced breakdown capability and isolation. Finally, an overview of the fierce fight of technology survival in terms of specific on-state resistance against breakdown voltage is given.     

Lithography for enabling advances in integrated circuits and devices

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.     

Scanning near-field optical microscopy as a tool for the characterization of multimode interference devices

We report the scanning near-field optical microscopy (SNOM) characterization of a 4 x 4 multimode interference (MMI) device working at a wavelength of 1.55 microm and designed for astronomical signal recombination. A comprehensive analysis of the mapped propagating field is presented. We compare SNOM measurements with beam-propagation-method simulations and thus are able to determine the MMI structure's refractive-index contrast and show that the measured value is higher than the expected value. Further investigation allows us to demonstrate that good care must be taken with the refractive-index profile used in simulation when one deals with low-index contrast structures. We show evidence that a step-index contrast is not suitable for adequate simulation of our structure and present a model that permits good agreement between measured and simulated propagating fields.     

Backgating in GaAs devices and integrated circuits

This paper reviews current understanding of backgating in GaAs integrated circuits and discusses approaches used to predict and mitigate its effect. Current theoretical approaches to explain backgating are reviewed and the impact of materials, process techniques, and design on backgating are also discussed. A standard backgating test structure and test proposed at the 1990 GaAs IC Symposium are described.     

Multipole electrical circuits in measurement devices

Methods for including multipole circuits in measurement devices are considered. We discuss the possible design choices for measurement circuitry and the corresponding measurement conversions. We present different models for determination of the characteristics of measurement converters using such circuitry. Translated from Izmeritel'naya Tekhnika, No. 8, pp. 14–19, August, 1999.     

Extreme sensitivity of the spin-splitting and 0.7 anomaly to confining potential in one-dimensional nanoelectronic devices

Quantum point contacts (QPCs) have shown promise as nanoscale spin-selective components for spintronic applications and are of fundamental interest in the study of electron many-body effects such as the 0.7 × 2e(2)/h anomaly. We report on the dependence of the 1D Landé g-factor g* and 0.7 anomaly on electron density and confinement in QPCs with two different top-gate architectures. We obtain g* values up to 2.8 for the lowest 1D subband, significantly exceeding previous in-plane g-factor values in AlGaAs/GaAs QPCs and approaching that in InGaAs/InP QPCs. We show that g* is highly sensitive to confinement potential, particularly for the lowest 1D subband. This suggests careful management of the QPC's confinement potential may enable the high g* desirable for spintronic applications without resorting to narrow-gap materials such as InAs or InSb. The 0.7 anomaly and zero-bias peak are also highly sensitive to confining potential, explaining the conflicting density dependencies of the 0.7 anomaly in the literature.     

Reliability problems in state-of-the-art GaAs devices and circuits

A review of the reliability status of GaAs discrete devices and integrated circuits is given. In the present survey of new devices and circuits it is shown that a significant number of reliability problems continue to persist.     

Logic devices and circuits based on giant magnetoresistance

In this paper, a new paradigm of performing logic operations is proposed. This new approach is based on the submicrometer giant magnetoresistance (GMR) effects. The key enabling features are nonvolatility, high GMR ratio, and control over the switching fields. The possible advantages of the new approach include ultrahigh density (because of the small device size), ultrahigh speed, nonvolatility, and radiation hardness. Key limitations are also identified. Several possible ways to surmount the limitations are also discussed. The proposed approach can, in principle, be applied to other material systems with similar characteristics     

Defect-tolerant architectures for nanoelectronic crossbar memories

We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of defective memory cell fraction. While our calculations are based on a particular ("CMOL") memory topology, with naturally segmented nanowires and an area-distributed nano/CMOS interface, for realistic parameters our results are also applicable to "global" crossbar memories with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development) may overcome purely semiconductor memories in useful bit density if the fraction of nanodevice defects (stuck-on-faults) is below approximately 15%, even under rather tough, 30 ns upper bound on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crossbar memories may be far superior to the densest semiconductor memories by providing, e.g., a 1 Tbit/cm2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better than those reported in literature earlier, including our own early work, mostly due to more advanced error correcting codes.     

Nanoscale synthesis and characterization of graphene-based objects

Graphene-based nano-objects such as nanotrenches, nanowires, nanobelts and nanoscale superstructures have been grown by surface segregation and precipitation on carbon-doped mono- and polycrystalline nickel substrates in ultrahigh vacuum. The dominant morphologies of the nano-objects were nanowire and nanosheet. Nucleation of graphene sheets occurred at surface defects such as step edges and resulted in the directional growth of nanowires. Surface analysis by scanning tunneling microscopy (STM) has clarified the structure and functionality of the novel nano-objects at atomic resolution. Nanobelts were detected consisting of bilayer graphene sheets with a nanoscale width and a length of several microns. Moiré patterns and one-dimensional reconstruction were observed on multilayer graphite terraces. As a useful functionality, application to repairable high-resolution STM probes is demonstrated.     

Nanoscale synthesis and characterization of graphene-based objects

Abstract

Graphene-based nano-objects such as nanotrenches, nanowires, nanobelts and nanoscale superstructures have been grown by surface segregation and precipitation on carbon-doped mono- and polycrystalline nickel substrates in ultrahigh vacuum. The dominant morphologies of the nano-objects were nanowire and nanosheet. Nucleation of graphene sheets occurred at surface defects such as step edges and resulted in the directional growth of nanowires. Surface analysis by scanning tunneling microscopy (STM) has clarified the structure and functionality of the novel nano-objects at atomic resolution. Nanobelts were detected consisting of bilayer graphene sheets with a nanoscale width and a length of several microns. Moiré patterns and one-dimensional reconstruction were observed on multilayer graphite terraces. As a useful functionality, application to repairable high-resolution STM probes is demonstrated.     

Utilization of operational amplifiers for raising the input impedance of measuring circuits

Summary The analysis and testing of a matching circuit consisting of two operational dc amplifiers have shown that it is possible by means of this circuit to match dc voltage circuits with a large internal resistance (up to 10 meg) to circuits with a small internal resistance (up to 10 kohm).     

SiC功率器件与电路中的栅介质技术

目前,宽带隙半导体材料SiC在功率MOS器件与电路方面的巨大优势一直没有很好地体现出来,这主要是受到SiC衬底上栅介质绝缘层的质量及界面特性方面的限制。本文在总结比较国际该领域研究现状的基础上,分析了碳元素的存在对介质层质量和界面态密度的影响,指出通过低温沉积氧化层以获得良好的界面质量,并通过高k介质的引入以提高介质层可靠性是今后SiC功率器件与电路研制中比较理想的栅介质制备技术。