The promising multi-bit/level programming operations for nano-scaled SONOS memory

In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90 nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 10⁴ program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.     

A single-sided PHINES SONOS memory featuring high-speed and low-power applications

A single-sided PHINES SONOS memory with hot-hole injection in program operation and Fowler-Nordheim (FN) tunneling in erase operation has been demonstrated for high program speed and low power applications. High programming speed (/spl Delta/V/sub t//program time) of 5 V/20 /spl mu/s, low power consumption of P/E, high endurance of 10 K, good retention, and scaling capability can be demonstrated.     

An 8-level 3-bit cell programming technique in NOR-type nano-scaled SONOS memory devices

An 8-level 3-bit cell programming technique is presented in NOR-type nano-scaled polycrystalline silicon-oxide–nitride-oxide-silicon (SONOS) memory devices. This new operating mode provides the double programming and sensing window over the traditional 4-level cell programming by using a double-side hot hole injection erasing. Compared with the 4-level cell, the storage density of the 8-level cell is greatly improved. However, the cycling endurance and retention properties are not obviously degraded until 1000 program/erase cycling.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>10⁴) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application     

Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EEPROM cells

An efficient erase technique is presented for SONOS EEPROM cells, using the concomitant hot-hole injection (HHI) at the drain and the source. Electrons trapped during the programming are thus fully eliminated throughout the entire channel, securing thereby a satisfactory cell endurance behavior. Additionally in the present HHI scheme the voltage applied at the common bulk terminal enables efficient erase in the entire erase sector. Also, HHI is quantitatively shown much more efficient for erase, compared with Fowler-Nordheim (F-N) tunneling. Finally, the elimination of trapped electrons throughout the entire channel is shown crucial for achieving a satisfactory cell endurance behavior.     

A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

A new technique of erasing nonvolatile memory (NVM) devices based on nitride storage (SONOS) with bottom oxide thickness in the range of 30 /spl Aring/ has been developed. Oxide thickness in this range is necessary to minimize the undesirable effects of gate disturb while still enabling a low-voltage operation to maximize the cost benefit of SONOS memories. To erase such bitcells, Fowler-Nordheim tunneling (FNT) is preferred over hot-hole injection (HHI) due to the less damaging nature of FNT. However, FNT alone cannot be used to erase the device completely due to erase saturation limitations. Hence, the new "combination-erase" technique combines both FNT and HHI erase to achieve a fast and controlled erase. Furthermore, by using FNT erase at higher field conditions, and HHI erase at lower field conditions, the reliability of the bitcell is also improved.     

An enhanced erase mechanism during channel Fowler-Nordheimtunneling in flash EPROM memory devices

An enhanced erase behaviour observed during the channel Fowler-Nordheim (FN) tunneling erase operation was examined in details. This enhanced erase occurs when a high p-well voltage is used, with the source and drain junctions of the cell left floating, during the erase operation. Our investigation indicates that the floating source and drain take on a high junction voltage during the p-well voltage transient. This causes transient band-to-band tunneling, and in some cases, junction avalanche breakdown, to occur in the source and drain junctions. As a result, hot-hole injection into the floating gate takes place to create this enhanced erase phenomenon     

A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 /spl mu/m/sup 2/ is fabricated based on 0.13-/spl mu/m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V/sub t/ in erase while programming is done by lowering a local V/sub t/ through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.     

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A novel 2-bit/cell nonvolatile memory (NVM) with metal-oxide-nitride-oxide-semiconductor (MONOS) asymmetric double gate (ADG) MOSFET structure is proposed. With the double gate structure, the two conducting channels provide the ability to store 2 bits in a cell. Program and erase can be performed by channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling respectively. The read operation and the array structure of the proposed novel NVM are also studied and described in this paper.     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

Pulse-$IV$ Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide

The transient behavior of SONOS-type devices was investigated for the first time using pulse- $IV$ technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC–$IV$ method. By using specific pulse-$IV$ setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 $muhbox{s}$ at low gate voltages ($≪$ 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.      

Performance Evaluation of Field-Enhanced P-Channel Split-Gate Flash Memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler–Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of$sim$2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.     

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.     

Temperature effect on read current in a two-bit nitride-based trapping Storage Flash EEPROM cell

The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V/sub T/ state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V/sub T/ state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.     

Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

We present a broad set of experiments on silicon nitride-based memories aimed at the investigation of the vertical position of the charge trapped in the nitride layer of silicon-oxide-nitride-oxide-semiconductor (SONOS) memories during program and erase in the tunneling regime. The results obtained for SONOS devices with conventional oxide-nitride-oxide and oxide-nitride-oxide-nitride-oxide gate stacks, as well as with high-top dielectric, have been validated by comparing different characterization techniques. It has been shown that, for SONOS cells, the charge centroid is located in the center of the silicon nitride layer, and its position is quite insensitive to the program or erase conditions and to the gate-stack composition.     

High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for nor-type Flash Memory

A dopant-segregated Schottky barrier (DSSB) FinFET silicon–oxide–nitride–oxide–silicon (SONOS) for nor-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant-segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for nor-type Flash memory with high-speed and low-power programming.      

Program Trapped-Charge Effect on Random Telegraph-Noise Amplitude in a Planar SONOS Flash Memory Cell

Program-charge effects in a SONOS Flash cell on the amplitude of random telegraph noise (RTN) are investigated. We measure RTN in 45 planar SONOS cells and 40 floating-gate (FG) cells in erase state and program state, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming, while an FG cell has identical RTN amplitudes in erase and program states at the same read-current level. A 3-D atomistic simulation is performed to calculate RTN amplitudes. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path-percolation effect caused by random discrete nitride charges.      

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler–Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.