超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

Wafer level chip scale packaging (WL-CSP): an overview

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. Rambus^TM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages     

一种CMOS驱动器的晶圆级芯片尺寸封装

采用晶圆级芯片尺寸封装(WLCSP)工艺完成了一款小型化CMOS驱动器芯片的封装.此WLCSP驱动器由两层聚酰亚胺(PI)层、重分配布线层、下金属层和金属凸点等部分构成.完成了WLCSP驱动器的设计,加工和电性能测试,并且对其进行了温度冲击、振动和剪切力测试等可靠性试验.结果表明,经过晶圆级封装的CMOS驱动器体积为1.8mm×1.2mm×0.35 mm,脉冲上升沿为2.3 ns,下降沿为2.5ns,开关时间为10.6 ns.将WLCSP的驱动器安装至厚度为l mm的FR4基板上,对其进行温度冲击试验及振动试验后,凸点正常无裂痕.无下填充胶时剪切力为20 N,存在下填充胶时,剪切力为200 N.     

Design and analysis of wafer-level CSP with a double-pad structure

Wafer level chip scale packaging (WLCSP) is very promising for the miniature of packaging size, the reduction of manufacturing cost, and the enhancement of the package's performance. However, the long-term board level reliability of integrated circuit (IC) devices using wafer level packaging with large distances from neutral point (DNP) is still not fully solved. This research proposes a novel, alternative WLCSP design for facilitating higher board level reliability. The main feature of the novel WLCSP is basically in its double-pad structure (DPS) design in the interface between solder joints and silicon chip. To characterize the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear finite element (FE) modeling technique is employed. Based on the FE modeling, the numerical accelerated thermal cycling (ATC) test is performed under the JEDEC temperature cycling specification. The validity of the proposed FE modeling is verified by using an optical measurement method Twyman-Green interferometer. By the derived incremental equivalent plastic strain, the cumulative cycles to failure in solder joints associated with these four WLCSP are assessed based on a modified Coffin-Manson relationship. The modeled fatigue life is compared against the experimental results that adopt a two-parameter Weibull distribution to characterize cycles-to-failure distribution. For comparison, the investigation also involves several existing types of WLCSP, including the conventional (C-WLCSP), the copper post (CP-WLCSP), and the polymer post (PP-WLCSP), and solder joint reliability performance among these WLCSP packages is extensively compared. The results demonstrate that the DPS-WLCSP design not only has potential for enhancing the corresponding solder joint reliability but is also particularly effective in manufacturing process and cost. And finally, some reliability-enhanced design guidelines are provided through parametric design of the DPS.     

晶圆尺寸级封装器件的热应力及翘曲变形

晶圆尺寸级封装(WLCSP)器件的尺寸参数和材料参数都会对其可靠性产生影响。使用有限元分析软件MSCMarc,对EPS/APTOS生产的WLCSP器件在热循环条件下的热应力及翘曲变形情况进行了模拟,分析了器件中各个尺寸参数对其热应力及翘曲变形的影响。结果表明:芯片厚度、PCB厚度、BCB厚度和上焊盘高度对WLCSP的热应力影响较为明显。其中,当芯片厚度由0.25mm增加到0.60mm时,热应力增加了21.60MPa;WLCSP的翘曲变形主要受PCB厚度的影响,当PCB厚度由1.0mm增加到1.60mm时,最大翘曲量降低了20%。     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations

The main investigation presented in this work is focused on the design and fabrication of redistribution in wafer level chip scale package (RDL in WLCSP) for high power device application. The design considers higher carrier loading incorporated with the dimensional broadening in both lateral and thickness direction of the metal redistribution layer. The lateral broadening shortens the channels of electrical isolation, while the thickness broadening evolves the conventional sputtering into the present electro-plating achieved Cu metallization layer. The innovation brings about the challenge for high power RDL in WLCSP. In this study, the interplay between structural design, process interactions, and possible solutions for high power RDL in WLCSP are presented. To address the arguments, two designs of experiment are conducted. We demonstrate the determinative influence factors, resultant from process interactions, toward the adhesive properties beyond the conventional wisdom.     

Effects of build-up printed circuit board thickness on the solderjoint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer     

低g值微惯性开关防粘连结构的设计与制作

低g值微惯性开关是一种感受惯性加速度、执行开关机械动作的精密惯性装置。为了解决开关芯片在清洗干燥过程中的粘连问题,提高器件的成品率,提出了防粘连的梯形凸台结构。该结构尺寸约为135μm×135μm×20μm,采用玻璃无掩膜湿法腐蚀技术在深约85μm的玻璃封盖底部实现。通过减小质量块与玻璃封盖底部的接触面积,弱化液体表面张力和范德华力的影响,避免了粘连现象的发生,使得低g值微惯性开关芯片在清洗干燥环节的合格率约达95%。采用MEMS体硅加工工艺和圆片级封装技术,完成了带有防粘连凸台结构的低g值微惯性开关的制作。玻璃无掩膜湿法腐蚀技术具有工艺简单、便于操作等优点,它的成功应用较好地满足了器件产业化的要求,为批量研制低g值微惯性开关提供了可靠的工艺基础。     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints ofwafer level chip scale package on buildup microvia printed circuit board

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies     

Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

A design assessment and optimization process for wafer-level chip size packages (WLCSP) is demonstrated. Besides the basic design, the thermal stress in WLCSPs with underfill and with increased standoff height, respectively, are analyzed by finite element method (FEM) simulations. The results are validated and a lifetime model is calibrated by experiments. Also, a WLCSP with stacked balls is optimized using the FEM models. Its total gain in lifetime over the basic design is estimated to reach 780%. WLCSP with optimum underfill endure 10 to 20 times longer than the basic WLCSPs. Soft underfill, however, has almost no effect on the critical inelastic strain. In addition to these practical results, the paper discusses some of the risks of FEM models (such as the singularity problem) and proposes ways of avoiding or overcoming them.     

C4NP-无铅倒装晶片焊凸形成生产工艺与可靠性数据

受控倒塌芯片连接新工艺是一种由IBM公司开发、由Suss Micro Tec公司推向商品化的新型焊凸形成技术。受控倒塌芯片连接新工艺采用各种无铅焊料合金致力于解决现有的凸台。形成技术限定,使低成本小节距焊凸形成成为可能。受控倒塌芯片连接新工艺是一种焊球转移技术,熔焊料被注入预先制成并可重复使用的玻璃模板(模具)。这种注满焊料的模具在焊料转入圆片之前先经过检查以确保高成品率。注满焊料的模具与圆片达到精确的接近后以与液态熔剂复杂性无关的简单工序转移在整个300mm(或300mm以下)圆片上。受控倒塌芯片连接新工艺技术能够在焊膏印刷中实现小节距凸台形成的同时提供相同合金选择的适应性。这种简单的受控倒塌芯片连接新工艺使低成本、高成品率以及快速封装周期的解决方法对于细节距FCiP以及WLCSP凸台形成均能适用。     

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. By using the solder ball shear test, the stress/strain-released behavior in the SOR structure is investigated in this research. On the other hand, a three-dimensional nonlinear finite element (FE) model for the ball shear test is established to assist the design of the package. The force-displacement curves from the FE analysis are compared with the experimental results to demonstrate the accuracy of the simulation. Likewise, the issue from element mesh density is also discussed herein. The investigation reveals that the SOR structure could highly decrease the damage in solder bumps from the ball shear test. Furthermore, the transferred stress/strain in the interconnect near the contact pad could be diminished through a suitable layout of redistribution lines.     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

Improvements of solder ball shear strength of a wafer-level CSP using a novel Cu stud technology

The solder ball shear test has been widely adopted in the electronics industry to estimate the strength of solder ball attachment of advanced electronic packages. A solder ball with low shear strength is usually considered as a weak solder joint in package reliability testing. Consequently, demands for increasing the solder ball shear strength have risen in recent years. This work attempts to enhance the solder ball shear strength of the wafer level chip scale package (WLCSP) by forming a Cu stud on the surface of the solder pad. The novel Cu stud design technology has been achieved by using a simple semiconductor manufacturing process. To investigate the impact of Cu stud, a three-dimensional (3-D) nonlinear finite element method is used for Cu stud design. Furthermore, the shear force-displacement curves, obtained by computational analysis, are compared with the experimental results to demonstrate the accuracy of the finite element models. This investigation also explores the effects of various parameters including the Cu stud's dimension, shape, and material properties on solder ball shear strength. The analytical results establish that a suitable size of Cu stud in a solder ball can effectively enhance the ball's shear strength.     

Quality factor measurement of micro gyroscope structure according to vacuum level and desired Q-factor range package method

A micro-machined gyro chip of gyroscope is normally packaged in specific vacuum level to get the specific quality factor(Q-factor). If the Q-factor is too high, frequency tuning and the approximate matching between driving and sensing comb structure become difficult, and if the Q-factor is too low, its sensitivity decreases. The optimum Q-factor of our gyro chip design is 4000 range. To get this range, we measured the drive mode Q-factor as vacuum level of our gyro chip and we found that the vacuum level of the desired Q-factor 4000 is in the range of 740 mTorr. Based on this data, we fabricate the wafer level package gyro chip of the desired Q-factor by controlled the basic pressure of package bonding chamber just prior to the bonding process. After wafer level package process, we measured Q-factor of whole samples. Among 804 samples, 502 packaged gyro chips are worked and the Q-factor of 67% samples is between 3500 and 4500 range.     

具有周边硅通孔的晶圆级芯片封装有限元分析

针对外围分布着硅通孔的晶圆级芯片封装结构,利用有限元分析软件ANSYS建立全局模型与次模型,在温度循环试验规范条件下将封装体与硅通孔结构分开进行仿真与探讨。了解模型受到温度载荷所产生的热力学行为。研究发现封装体在经历温度循环试验后所产生的位移呈现圆形对称分布,结构在高温时向外翘曲,在低温时向内弯曲;重布线层在与锡球交界处会产生明显的应力集中。硅通孔结构中铜垫片越接近开孔所受应力越大;硅通孔结构的重布线层部分,应力集中在转角处以及靠近钝化保护层交界处。     

Interfacial reaction study on a solder joint with Sn-4Ag-0.5Cu solder ball and Sn-7Zn-Al (30 ppm) solder paste in a lead-free wafer level chip scale package

The interfacial reactions of solder joints between the Sn-4Ag-0.5Cu solder ball and the Sn-7Zn-Al (30 ppm) presoldered paste were investigated in a wafer level chip scale package (WLCSP). After appropriate surface mount technology (SMT) reflow process on the printed circuit board (PCB) with organic solderability preservative (Cu/OSP) and Cu/Ni/Au surface finish, samples were subjected to 150°C high-temperature storage (HTS), 1,000 h aging. Sequentially, the cross-sectional analysis is scrutinized using a scanning electron microscope (SEM)/energy-dispersive spectrometer (EDS) and energy probe microanalysis (EPMA) to observe the metallurgical evolution in the interface and solder buck itself. It was found that Zn-enriched intermetallic compounds (IMCs) without Sn were formed and migrated from the presolder paste region into the solder after reflow and 150°C HTS test.