变频器的功能设置概述（三） 第2讲 变频器的频率给定方式

所谓频率给定方式,就是调节变频器输出频率的具体方法,也就是提供给定信号的方式。变频器常见的频率给定方式主要有：操作器键盘给定、接点信号给定、模拟信号给定、脉冲信号给定和通讯方式给定等。这些频率给定方式各有优缺点,必须按照实际的需要进行选择设置,同时也可以根据功能需要选择不同频率给定方式之间的替加和切换。本文主要阐述的就是变频器的这几种频率给定方式。     

变频器减速过程加入母线电压闭环的方法

工业现场中,变频器减速时间设置过短可能使变频器报过压故障而停机,针对这种情况,本文提出了一种方案,减速过程在原有控制的基础上增加一个直流母线电压闭环环节,对矢量控制,将该环节根据条件判断并联在速度环上,电压环保证在减速过程不出现过压,速度环保证对速度的精确控制。对V/F控制,将该环节叠加到减速斜坡输出上,减少直流母线过压的概率。     

两辊矫直机的ABB变频器主从控制应用

ACS800变频器在两辊矫直机的应用中,为了2台400kW交流电动机在同步运行的机构之间建立合理的负载分配关系,充分发挥各电动机的转矩输出能力,使其的负荷达到均匀平衡,需要进行两辊间力矩给定控制,使上下两辊受力相同,提高矫直质量、平直度,降低设备损坏率.本文讲述了江阴兴澄特种钢铁有限公司轧钢一台矫直机由原来的纯速度控制技改为力矩主从控制的方法.     

浅谈变频器控制正反转线路的研究

通过研究变频器实验系统的功能及应用实例的解析使读者掌握变频器的基础知识,根据给定的任务要求,绘制变频器控制电路图,对元件在试验板上进行合理布置和安装,达到美观紧固的要求,通过操作变频器键盘,正确设置参数,完成通电调试。     

一种自适应斜坡补偿电路的设计与实现

提出了一种应用于电流型DC-DC转换器的自适应斜坡补偿电路.在分析斜坡补偿原理的基础上,提出了一种动态的斜坡补偿方法.该方法利用跨导线性环电路对补偿电流信号进行叠加,无需外加引脚引入输出电压,从而减小了芯片封装尺寸,以较少的电路使引入的斜坡补偿对系统带载能力和瞬态响应的负面影响减至最小.此电路采用UMC BCD工艺,在升压型DC-DC转换器2V转换8V的条件下,带载能力达到300mA,负载调整率为6.7mV/A.     

变频器的功能设置概述（四） 第3讲 变频器的运转指令方式

变频器的运转指令方式是指如何控制变频器的基本运行功能，这些功能包括启动、停止、正转与反转，正向电动与反向点动，复位等。与变频器的频率给定方式一样，变顿器的运转指令订式也有操作器键盘控制，端子控制和通讯控制三种。这些运转指令方式必须按照实际的需要进行选择设置，同时也可以根据功能进行相互之间的方式切换。本文主要闸述的就是变频器的运转指令方式。     

一种自适应斜坡补偿电路的设计与实现

提出了一种应用于电流型DC-DC转换器的自适应斜坡补偿电路.在分析斜坡补偿原理的基础上,提出了一种动态的斜坡补偿方法.该方法利用跨导线性环电路对补偿电流信号进行叠加,无需外加引脚引入输出电压,从而减小了芯片封装尺寸,以较少的电路使引入的斜坡补偿对系统带载能力和瞬态响应的负面影响减至最小.此电路采用UMC BCD工艺,在升压型DC-DC转换器2V转换8V的条件下,带载能力达到300mA,负载调整率为6.7mV/A.     

转炉倾动系统传动及控制

湖南华菱湘潭钢铁有限公司宽厚板厂转炉倾动传动系统采用西门子低压变频器,由一套西门子S7-400PLC进行外部信号的采集及传动变频器的启停及主站给定信号的控制,同时对变频器的反馈信号做出处理。本文介绍了电控系统的基本组成,传动系统的力矩平衡控制及主站的选择。着重介绍了SIMOLINK在该系统中的应用。     

薄栅氧化层斜坡电压TDDB击穿参数的研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路的可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。本次实验主要是通过斜坡电压实验来研究薄栅氧化层的TDDB,测出斜坡电压时氧化层的击穿电压、击穿电荷以及击穿时间,研究了斜坡电压情况下,栅氧化层击穿电荷、击穿电压和外加电压斜率等击穿参数间的依赖关系。     

基于变频器的造纸机传动系统设计

文章是应用ABBACS800变频器设计的造纸机电气传动控制系统，通过对硬件、软件的设计负荷分配、速度链设计等问题进行较为详细地描述。较好的实现了系统控制要求，这种基于PLC和变频器的全数字控制系统适用高速纸机的高速度、高可靠性控制性能的需要。     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

A mixed-mode PWM controller

In this article, a mixed-mode (MM) PWM controller for dc–dc power converter topologies is presented and analysed. Compared to the conventional peak current-mode (PCM) controller, the proposed controller exhibits better results in terms of robustness towards load and reference voltage variations while maintaining better dynamic response. In the PCM controller, the control signal is a combination of inductor or, most often, switch current and a suitable compensation ramp which in the most common applications is constant. In the proposed controller, the constant compensation ramp has been replaced by a ramp voltage which is proportional to the output voltage taking into consideration the output voltage variations during load and reference transients. Consequently, the proposed controller, which exhibits the same advantages as with the PCM controller, additionally exhibits better load and reference performance for constant output voltage and output tracking applications without increasing the cost and the complexity of the control circuit. Finally, in order to verify the theoretical analysis and conclusions, both control schemes (i.e. PCM and MM) have been simulated and experimentally tested using a 75 W buck converter unit.     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Limitations and noise in interferometric systems using frequency ramped single-mode diode lasers

Frequency ramped diode laser sensing and measurement systems suffer from a variety of limitations and noise sources. Nonlinearities in the frequency ramp produce unwanted sidebands in the frequency spectra of the system output and make accurate distance determination difficult in the frequency domain. Thermally induced drifts in the laser frequency prohibit long-term sensitive phase measurements even with a reference interferometer. It is shown that phase noise due to the fundamental linewidth of the diode laser and not bias current noise determines the noise floor of most FMCW systems in the regimes away from (1/f) noise. Time domain techniques suffer from low resolution because only a few data points can be taken during each frequency ramp and thus achieve poor averaging of the phase noise. The signal to noise ratio (SNR) of frequency ramped systems is shown to be lower (10-30 dB) than the theoretical prediction for an unmodulated heterodyne system, which was substantiated by showing that the minimum detectable phase is somewhat higher than that predicted by the idealized model.     

Dielectric breakdown distributions for void containing silicon substrates

Distributions of gate oxide failure in various types of silicon substrate materials have been investigated for a wide range of oxide thicknesses. Silicon substrates containing various well-characterized void distributions along with defect-free materials were tested using special low-series resistance capacitor structures. Results of both ramped field tests of variable ramp rate and constant field tests were performed and analyzed within the framework of Weibull statistics. Ramped field tests are not “time zero dielectric breakdown” tests as is commonly asserted. They can in fact be very useful in extrapolating time dependent failure. The same set of Weibull parameters can be used to describe both ramped field and constant field wearout tests if an appropriate model for the time dependent damage accumulation during the field ramp is used. There are implications for reliability predication and the burn-in screening of device populations containing such defects.     

数字接收机中超高速A／D转换电路的PCB设计

随着大规模集成电路和数字信号处理技术的迅速发展，雷达接收机和电子战接收机的数字化已是一种必然趋势，A／D变换器是决定数字接收机性能的关键部件之一，文中结合一种采样率可达1GSPS的A／D转换电路的设计，重点介绍了高速高频PCB设计的一些规则、注意事项和经验。     

A 12-bit monolithic 70 ns DAC

Describes a 12-bit monolithic digital-to-analog converter with 70 ns settling time and a low output glitch content. The device is fabricated on a standard high speed digital process and needs no post-processing trimming to achieve the required accuracy and monotonicity. The output from this device is in the form of two complementary output currents, which may be terminated in resistive loads or amplified by a virtual earth input stage. Included on the chip are a temperature compensated voltage reference and reference loop amplifier. Essential external components are limited to a single current range setting resistor and decoupling/compensation capacitors.     

Novel Design for High Speed and Resolution Delta-sigma A/D Converter

The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta- sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching（DEM） and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.     

Time domain modelled ADC BIST with ramp noise projection

This paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy.     

A novel droop method for converter parallel operation

For the converter parallel operation, the current sharing between modules is important for the reliability of the system. Among several current sharing schemes, the droop method needs no interconnection between modules, which implies true redundancy. But the droop method has poor voltage regulation and poor current sharing characteristics. In this paper, a novel droop method is proposed for the converter parallel operation, which adaptively controls the reference voltage of each module. This greatly improves the output voltage regulation and the current sharing of the conventional droop method. The analysis of the proposed method and design procedure are provided and experimental results verify the excellent performance of the proposed method