Control of topography and morphology for channel SiGe by in-situ HCl etching for future CMOS technologies with high-K metal gate

In high-K metal gate-first integration for future CMOS technologies an epitaxial SiGe layer in the P-channel is applied to modulate V_T. This results in an unwanted elevation of the P-channel challenging particularly gate patterning. In this work, an in-situ HCl etching process prior to deposition of the channel SiGe for gate-first integration of HKMG has been studied. By in-situ HCl etching prior to epitaxial deposition (recessed cSiGe) the topography is clearly reduced with excellent epitaxial quality. The morphology of channel SiGe particularly for very small feature sizes is significantly improved by recessing the P-channel prior to epitaxial deposition. The flat topography shows a clear benefit for the gate-first integration. The topography driven P-channel leakage was reduced by one order of magnitude for recessed channel SiGe.     

Velocity of surface carriers in inversion layers on silicon

Velocity-field curves for surface free-carriers in silicon are determined from measurements on resistivegate IGFETs. The measurements were performed on n-channel devices fabricated on both (100) and (111) substrates and on p-channel devices fabricated on (100) substrates. The channel length of the devices is ～8 μm and the impurity concentration of the substrates is ～ 10¹⁵ cm^?3. The dependence of velocity on the field strength along the channel is found to be well approximated by an empirical relationship involving three parameters: low-field mobility μ₀, a critical field $\text{E}{}_{\mathrm{cy}}$ signalling the onset of velocity saturation, and a parameter α that determines the curvature between the constant-mobility and constant-velocity branches of the curve. The curve-fitting parameters are given in tabular form for the two n-channel and one p-channel systems studied. The dependence of the velocity-field curves on temperatures in the range 100–350K is also reported.     

A new integrated voltage-controlled negative resistance device-Lambda MOSFET

A new Λ-type voltage-controlled negative resistance device called the “Lambda MOSFET” is presented, which consists of three integrated n(p)-channel enhancement mode metal-oxide-silicon field effect transistors. The main integrated circuit construction of the Lambda MOSFET is to connect an inverter of the n(p)-channel enhancement mode MOSFET with load operated at the saturation region (NELS) and a n(p)-MOS driver, which can be easily fabricated by existing planar MOSFET technologies. The operational principles and the characteristics of the proposed new device are discussed.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Excess high frequency noise and flicker noise in MOSFETs

The noise parameter α=R_ng_m, where R_n is the noise resistance and g_m the transconductance, was measured for n- and p-channel MOSFETs as a function of frequency with the temperature T as a parameter. At lower frequencies α varies as 1/f, as expected for flicker noise, whereas at higher frequencies α attains a limiting value α_∞ that is larger than expected for thermal noise. Arguments are presented whether this high-frequency noise can be hot electron noise. The flicker noise resistance R_mf has a much stronger temperature dependence for n-channel than for p-channel devices; this is related to the energy dependence of the surface state distribution in the forbidden gap.     

Noise due to donors in n-channel silicon JFETs

We have measured the noise due to donors in n-channel silicon JFETs at temperatures near liquid nitrogen temperature. The noise showed an activation energy of about 1.3E₀, where E₀ is the activation energy of the donor centers. This is compatible with theory.     

The A-MOSFET—A majority carrier accumulation MOSFET

A novel MOSFET device structure is proposed that operates on the principle of majority carrier accumulation in the channel. The basic current equation is obtained for an n-channel structure.     

Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77 K to 300 K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μ_e) and hole (μ_h) mobilities, both at about 1.6 cm²/V s. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μ_e indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μ_e and μ_h both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230 K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T < 210 K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.     

The low temperature strain sensitivity of MOS transistors

A theoretical and experimental study has been made of the effect of strain on metal oxide silicon transistors (MOST's) at low temperatures. The quantization of momentum of electrons which occurs in the inversion layer of n-channel MOST's alters the piezoresistance effect, and an analysis is given for the case of a single quantized sub-band. This analysis shows that under certain rather restrictive conditions the piezoresistance of the drain to source resistance of MOST's fabricated in the (111) plane of silicon can be independent of temperature. Experimental results were obtained from both n^?and p-channel transistors; a maximum sensitivity to strain usually occurred at about 100 K. At lower temperatures the strain sensitivity could be made fairly insensitive to temperature changes under appropriate conditions. However it is unlikely that strain gauges made from MOST's could rival conventional gauges for the measurement of strain at low temperatures.     

Threshold shift of p-channel transistors by boron implantation and the C-V characteristics of the corresponding mos structures

Short p-channel transistors for scaled CMOS circuits are fabricated using double implantations with phosphorus and boron ions. Deep phosphorus channel implantation is required for increasing the channel punch-through voltage, while shallow boron implantation is used to adjust the device threshold voltage for p-channel transistors with n + poly as the gate electrode. The effect of the boron dose and the sub-surface junction depth on the device characteristics, especiallly the C?V characteristics, is investigated.The capacitance dispersion with respect to frequency, which is observed for MOS diodes with large boron dose or deep boron depth, will be discussed in detail. This phenomenon is explained by the majority carrier modulation at the sub-surface junction associated with the boron implanted channel. The effect of the non-uniform phosphorus channel doping on the measured C?V characteristics will also be examined. The technique of the one-dimensional calculation of the channel potential distribution is presented to show the correlation of the implanted boron dose and the observed abnormal C?V characteristics.     

A re-examination of practical performance limits of scaled n-channel and ϱ-channel MOS devices for VLSI

The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2 μm gate length including all of the major effects such as source/drain series resistance, mobility degradation due to both parallel and perpendicular fields, and inversion layer capacitance under three different power supply scenarios. From the degradation factor of triode gain and drain saturation current, the relative contribution of each parasitic effect on device performance degradation has been examined. Based on these calculations, some modifications to straight-forward scaling are considered.     

Non-functionalized soluble diketopyrrolopyrrole: Simplest p-channel core for organic field-effect transistors

We report the synthesis, characterization and behavior in field-effect transistors of non-functionalized soluble diketopyrrolopyrrole (DPP) core with only a solubilizing alkyl chain (i.e. –C₁₆H₃₃ or –C₁₈H₃₇) as the simplest p-channel semiconductor. The characteristics were evaluated by UV–vis and fluorescence spectroscopy, X-ray diffraction, cyclic voltammetry (CV), thermal analysis, atomic force microscopy (AFM) and density functional theory (DFT) calculation. For top-contact field-effect transistors, two types of active layers were prepared either by a solution process (as a 1D-microwire) or thermal vacuum deposition (as a thin-film) on a cross-linked poly(4-vinylphenol) gate dielectric. All the devices showed typical p-channel behavior with dominant hole transports. The device made with 1D-microwiress of DPP-R18 showed field-effect mobility in the saturation region of 1.42 × 10^?2 cm²/V s with I_ON/I_OFF of 1.82 × 10³. These findings suggest that the non-functionalized soluble DPP core itself without any further functionalization could also be used as a p-channel semiconductor for low-cost organic electronic devices.     

An accurate model for a depletion mode IGFET used as a load device

An accurate model has been described for an n-channel, silicon gate, depletion mode insulated gate field effect transitor (IGFET), in configuration most often used in LSI design (V_GS=OV). The model is derived from basic semiconductor charge analysis, approximating the profile of the redistributed implanted impurities in the channel. Excellent agreement with experimental results is shown. This model has the potential to accurately predict the charge capacity behavior in storage cells, in very high density random access memories, where “pseudo depletion mode” devices are used.     

Mosfets with low threshold value

A technique for fabricating p-channel enhancement mode molybdenum gate MOSFETs with low threshold voltage is outlined.     

Analysis of the quasi-saturation region of high voltage VDMOS devices

The effect of the epitaxial layer on the quasi-saturation region of the I_D(V_D) characteristic of a high voltage n-channel VDMOS structure is analysed. The proposed model takes into account the cylindrical shape of the P-well/N⁻-epilayer junction and the pinching effect of the current between neighbouring cells.     

High-performance C60 and picene thin film field-effect transistors with conducting polymer electrodes in bottom contact structure

C₆₀ and picene thin film field-effect transistors (FETs) in bottom contact structure have been fabricated with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS) electrodes for a realization of mechanical flexible organic FETs. The C₆₀ thin film FETs showed n-channel enhancement-type characteristics with the field-effect mobility μ value of 0.41 cm² V^?1 s^?1, while the picene thin film FET showed p-channel enhancement-type characteristics with the μ of 0.61 cm² V^?1 s^?1. The μ values recorded for C₆₀ and picene thin film FETs are comparable to those for C₆₀ and picene thin film FETs with Au electrodes.     

1/<Emphasis Type="Italic">f</Emphasis> noise in metal insulator semiconductor transistors with different conductivity types and different topological dimensions of the channel

An experimental investigation of 1/f noise in metal insulator semiconductor transistors with different types of channel conductivity and different topological sizes of the gate region is presented. The transistors are produced on the basis of the standard 1.2-μm complementary metal oxide semiconductor technology and can be used as reading elements in 2D multielement detectors of infrared radiation. The level of 1/f noise is determined in relation with the channel conductivity type. It is shown that the p-channel transistors exhibit a lower level of 1/f noise compared to that of the n-channel transistors (by about one order of magnitude). The dependence of 1/f noise on the topological size of the gate region is obtained. The transistors with the smallest channel width are found to produce the highest noise level.     

Most digital logic circuits in silicon films deposited on sapphire substrates

Details are given of the construction and performance of MOS transistors, logic elements and digital integrated circuits fabricated in silicon layers grown on sapphire substrates and processed on a p-channel enhancement MOST process. P-channel enhancement MOSTs with parameters similar to those of bulk silicon MOSTs, linear resistors with a high sheet resistivity and non-linear resistors are obtained. The use of non-linear resistors is shown to give static logic circuits with operating speeds 2–4 times faster than linear resistors. In addition node capacitance is reduced, the thick oxide MOST is eliminated and dielectric isolation between devices is obtained. Experimental and computer simulated results are given for the performance of a range of logic elements and circuits.     

Dicyanomethylene-quinoid vs. dicyanovinyl-benzenoid organic semiconductors: Understanding structure-property correlations in mesomerism-like forms

Understanding two mesomerism-like forms (quinoid vs. benzenoid structures) over organic semiconductors (OSCs) is essential for achieving high electronic device performance. Herein, we report the synthesis as well as the comparative physicochemical, microstructural, and charge-transporting analysis of dicyanomethylene-quinoid versus dicyanovinyl-benzenoid OSCs based on benzo[1,2-b:4,5-b′]dithiophene (BDT) units (DCM-Q-BDT and DCV-B-BDT). The electron-deficient nature of the quinoid structure in DCM-Q-BDT can lower the LUMO level and bandgap relative to the benzenoid analogy DCV-B-BDT. Top-gate/bottom-contact (TG/BC) field-effect transistors (OFETs) based on DCM-Q-BDT show not only the maximum electron mobility up to 0.23 cm²/V.s without requiring post-annealing treatments, but also demonstrate excellent air stability (half-life times of drain current ≈ 35 h) without any encapsulation. The superior n-channel performance for DCM-Q-BDT is due to the anisotropic orientation, high degree of the crystallinity, and low-lying LUMO induced by the quinoid structure. Our study shows underlying structure–property relationships in quinoid over benzenoid OSCs while demonstrating promise in n-channel OFETs.