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1.
Sewook Hwang Junyoung Song Sang-Geun Bae Chulwoo Kim 《Analog Integrated Circuits and Signal Processing》2014,81(2):461-469
A 3 Gb/s wireline transmitter (Tx) with a tapless pre-emphasis current-mode logic output driver is presented in this paper. The proposed output driver can support 2.5, 6 and 10 dB pre-emphasis without any additional current tap. It can reduce the current consumption of the output driver by 30 %. The 1.5 GHz phase-locked loop (PLL), multi-phase generator, and 26-to-1 serializer are utilized to serialize 26-bit parallel data to 1-bit 3 Gb/s serial data stream. The rms and peak-to-peak jitters of PLL are 2.97 and 22.5 ps, respectively. The eye opening of the proposed output driver at 3 Gb/s is 0.8UI with a 10 dB loss channel. The current consumption of the output driver is only 5.14 mA, and the Tx is 9 mA. The area of the Tx is 0.72 mm2 using the 0.11 μm CMOS process. 相似文献
2.
T. Torounidis M. Westlund H. Sunnerud B.-E. Olsson P.A. Andrekson 《Photonics Technology Letters, IEEE》2005,17(2):312-314
Short return-to-zero pulses (/spl sim/2 ps) are generated at bit rates of 40, 80, and 160 Gb/s using a fiber-optical parametric amplifier. The performance of the parametric pulse source is evaluated both back-to-back and in a 110-km transmission link. A receiver sensitivity of -33 dBm back-to-back was achieved after demultiplexing from 160 to 10 Gb/s. The power penalty at 160 Gb/s due to 110-km transmission was less than 2 dB. Very short pulses (0.5 ps) were also achieved when using the parametric amplifier as a compressor. 相似文献
3.
This paper proposes an open‐loop clock recovery circuit (CRC) using two high‐Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual‐mode operation. The DR filters are fabricated to obtain high Q‐values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak‐to‐peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo‐random binary sequence (PRBS) data with a word length of 231?1 are less than 2.0 ps and 0.3 ps, respectively. The peak‐to‐peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error‐free operation of the 40 Gb/s‐class optical receiver with the dual‐mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates. 相似文献
4.
Tamamura M. Shiotsu S. Hojo M. Nomura K. Emori S. Ichikawa H. Akai T. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1575-1578
A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed 相似文献
5.
采用自行研发的4英寸InGaP/GaAs HBT技术,设计和制造了10Gb/s光调制器驱动电路.该驱动电路的输出电压摆幅达到3Vpp,上升时间为34.2ps(20~80%),下降时间为37.8ps(20~80%),输入端的阻抗匹配良好(S11=-12.3dB@10GHz),达到10Gb/s光通信系统(SONET OC-192,SDH STM-64)的要求.整个驱动电路采用-5.2V的单电源供电,总功耗为1.3W,芯片面积为2.01×1.38mm2. 相似文献
6.
Inhwa Jung Daejung Shin Taejin Kim Chulwoo Kim 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(10):773-777
A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents. 相似文献
7.
利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。 相似文献
8.
Che-Fu Liang Sy-Chyuan Hwu Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2008,43(5):1217-1226
A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm2. The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 27-1 PRBS. The measured bit error rate for a 10 Gb/s 27-1PRBS is less than 10-12. 相似文献
9.
Suzuki K. Iwatsuki K. Nishi S. Samwatari M. Kitoh T. 《Photonics Technology Letters, IEEE》1994,6(3):352-354
0.8 ps TL pulses are successfully generated from a gain-switched DFB-LD by adiabatic soliton compression using a dispersion decreasing fiber (DDF). The compression ratio can be controlled using the peak input power into the DDF. We obtain a 10×2n Gb/s pulse stream by optically multiplexing the compressed pulses with a Mach-Zehnder (MZ) interferometer type multiplexer, in which n can be freely selected from 1 to 4 by controlling the coupling ratios of the couplers in the MZ interferometers. By using the demonstrated techniques, we can multiplex the initial pulse stream up to 160 Gb/s at the noninterfering duty factor of 0.2 相似文献
10.
《Solid-State Circuits, IEEE Journal of》2009,44(3):775-783
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12.
Kuriyama Y. Morizuka K. Akagi J. Asaka M. Tsuda K. Obara M. 《Solid-State Circuits, IEEE Journal of》1991,26(6):876-879
High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively 相似文献
13.
Melle S. Dodd R. Grubb S. Liou C. Vusirikala V. Welch D. 《Communications Magazine, IEEE》2008,46(2):S22-S29
This article describes how bandwidth virtualization can enable transmission of ultra-high bandwidth 40 Gb/s and 100 Gb/s services over existing optical transport networks independently of the underlying network infrastructure. An overview of the technology alternatives available to enable high-bandwidth service transport is provided, along with a discussion of the relative merits of different approaches. The authors describe how wavelength division multiplexing, using large- scale photonic integrated circuits combined with the use of a digital virtual concatenation mapping protocol, can be used to enable decoupling of 40 Gb/s and 100 Gb/s service provisioning from the underlying optical link engineering, thereby enabling bandwidth virtualization. Real-world implementation examples of bandwidth virtualization are provided, including 40 Gb/s service transmission over a 2000-km fiber link with 65 ps of peak PMD, a field trial of 40 Gb/s service transmission over an 8477-km trans-oceanic network, and finally a field trial of a pre-standard 100 gigabit Ethernet service transmission over a 4000-km terrestrial long-haul network. 相似文献
14.
对40 Gb/s OTDM系统中光纤光栅色散补偿器进行偏振模色散补偿的研究 总被引:3,自引:2,他引:1
改变光纤光栅紫外曝光系统 ,在相位掩模板后插入一个旋转装置 ,使得光纤在制作过程中可以进行某种旋转。通过这种方法制作的光纤光栅偏振模色散减小到平均差分群时延 (DGD)约为 0 2ps,而没加旋转制作的光纤光栅平均DGD约为 18 2 ps。采用两个这种低偏振模色散 (PMD)的光纤布拉格光栅 (FBG) ,成功地在 4 0Gb/s光时分复用 (OTDM)系统中补偿了约 2 0 4 0 ps的色散 ,该系统在经过 12 2km普通单模光纤传输后 ,未发现PMD的影响 ,传输功率代价小于 1 4dB。 相似文献
15.
Masuda T. Ohhata K. Shiramizu N. Ohue E. Oda K. Hayami R. Shimamoto H. Kondo M. Harada T. Washio K. 《Solid-State Circuits, IEEE Journal of》2005,40(3):791-795
A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction. 相似文献
16.
Suzaki M. Yamanaka N. Hirata M. Kikuchi S. 《Solid-State Circuits, IEEE Journal of》1990,25(1):155-159
An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI 相似文献
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18.
低电压差分信号(LVDS)是串并转换电路(SerDes)的一种主流接口技术.本文设计并实现了一种适合于8B/10B编码串并转换电路的LVDS接收器(Receiver).本设计的指标完全兼容IEEEStd1593.3-1996标准.它支持最大0.05 V至2.35 V的共模电平输入范围,最小100 mV的差模输入,能够在至少40英寸FR4带状线上达到1.6 Gb/s的接收速率,平均功耗3 mw.电路设计基于0.18μm1.8 V/*3.3 VCMOS工艺,同时采用了3.3 V器件和1.8 V器件. 相似文献
19.
Jun-Chau Chien Liang-Hung Lu 《Microwave and Wireless Components Letters, IEEE》2006,16(10):558-560
By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-/spl mu/m CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps. 相似文献
20.
Rauschenbach G.A. Hall K.L. Livas J.C. Raybon G. 《Photonics Technology Letters, IEEE》1994,6(9):1130-1132
An all-optical pulse width and wavelength converter is demonstrated using a nonlinear optical loop mirror. The conversion of a 10 Gb/s, 8 ps pulse width data stream at 1551 nm to a 23 ps pulse width data stream at 1543 nm is demonstrated. The control pulse energy required for switching is 10 pJ. Bit-error-rate measurements are presented 相似文献