Device Requirements for Optical Interconnects to Silicon Chips

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.     

Scaling theory in modern VLSI

Discusses the scaling rules for VLSI that pertain to the total wire length and the clock speed. The analysis indicates that the total wire length is not increasing as rapidly as standard scaling theory would indicate. This results from over-scaling of the cell size reduction from one generation to the next (as predicted by Moore [1975]). However, the total wire length is still increasing at a rate that will cause significant power dissipation in the interconnects and indicates the need for new locally interconnected architectures. Moreover, the over-scaling of cell size reduction also raises the possible limitations that arise as the cell size is reduced faster than the gate length. We also discussed the effects of scaling on on-die clock speed. While gate-array clock speeds are scaling slower than the scaling rules would predict (a problem for large multi-chip architectures), clock speeds in modern VLSI chips track the scaling rule quite accurately     

Solid state [Technology 1998 analysis and forecast]

Even as lithography further miniaturizes IC features, other advances are finessing device designs and the means of fabrication. Revisionist microprocessor architectures herald greater efficiency of instruction execution. Multilevel memory cells are doubling the storage density of flash chips. This year will see IC performance enhanced by the first implementations of copper interconnects. Beyond copper, engineers developing optical interconnections are waiting in the wings to show what their technology can do. Scientists find no dearth of potential lithographic tools for coming IC generations. To the contrary, industry leaders have several candidates to pick from: X-ray, projection electron-beam, extreme ultraviolet, and ion projection lithographies. But no technology has overcome all its obstacles and it is not at all clear which if any of the alternatives will emerge as the industry's tool of choice     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

System-level design consideration and optimization of through-silicon-via inductor

Due to the slow scaling of board and package technology, on-chip inductor has shown promising potential to enable more compact design and smaller parasitics for inductor-based designs, such as voltage regulator, resonant clocking, filter, etc. On the other hand, conventional on-chip 2D spiral inductor must be placed on the top metal layers, thereby consuming significant routing resources for global interconnects. Moreover, it may need more dedicated shielding to prevent unnecessary coupling, which further increases its occupied area. With the popularity of 2.5D and 3D chip architecture, Through-Silicon-Via (TSV) has been widely used, a significant portion of which are placed for thermal/manufacturability/reliability purposes. Thus, those redundant TSVs can be utilized to form the on-chip inductor for 2.5D/3D chips, with lower footprint and higher inductance density compared from the conventional spiral inductor. Unlike prior works focusing on the inductor itself, this paper discusses the optimization and application of such TSV-inductor from system perspective, including the optimization options and its design considerations. The possible design options including physical parameters, architecture and materials, to optimize the TSV-inductor are thoroughly investigated. Based on that, we further study a few key design scenarios to evaluate the design impact with use of such TSV-inductor and provide the design guidelines for its application in actual system designs.     

Light emission from silicon: Some perspectives and applications

Research on efficient light emission from silicon devices is moving toward leading-edge advances in components for nano-optoelectronics and related areas. A silicon laser is being eagerly sought and may be at hand soon. A key advantage is in the use of silicon-based materials and processing, thereby using high yield and low-cost fabrication techniques. Anticipated applications include an optical emitter for integrated optical circuits, logic, memory, and interconnects; electro-optic isolators; massively parallel optical interconnects and cross connects for integrated circuit chips; lightwave components; high-power discrete and array emitters; and optoelectronic nanocell arrays for detecting biological and chemical agents. The new technical approaches resolve a basic issue with native interband electro-optical emission from bulk Si, which competes with nonradiative phonon- and defect-mediated pathways for electron-hole recombination. Some of the new ways to enhance optical emission efficiency in Si diode devices rely on carrier confinement, including defect and strain engineering in the bulk material. Others use Si nanocrystallites, nanowires, and alloying with Ge and crystal strain methods to achieve the carrier confinement required to boost radiative recombination efficiency. Another approach draws on the considerable progress that has been made in high-efficiency, solar-cell design and uses the reciprocity between photo- and light-emitting diodes. Important advances are also being made with silicon-oxide materials containing optically active rare-earth impurities.     

Electrical interconnects revitalized

Models of electrical interconnects, including inductance and skin effect, are reviewed. The models are used for estimating the performance of electrical interconnects, particularly related to delays, data rates, and power consumption for off-chip and on-chip interconnects and for clock distribution. It is demonstrated that correctly utilized, electrical interconnects do not severely limit chip or circuit board capacity. Delays, data rates, and power consumption of electrical interconnects within a circuit board are acceptable and superior to optical alternatives.     

Integrated Systems [systems on a chip]

Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O's and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The “composite IC” is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate “snap-together” physical and electrical interfaces with high reproducibility. While similar to conventional MCM's, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing     

Gasping the impact of on-chip inductance

The rapid advancements in process technology and heightening market pressures for functional integration are resulting in large VLSI chips operating at steadily increasing frequencies. The number of long global wires per chip has been continuously increasing with time. These wires carry high-frequency currents and have low resistance. This low resistance is due to the use of thick and wide interconnects at higher metal layers. Additionally, superior conducting materials such as copper have been introduced in order to keep the resistance and the RC delay of global lines small. These factors have led to a continuous increase in the importance of inductance, which has emerged as a standard factor that designers must take into consideration when designing high-performance chips in deep-submicron technologies. In this paper, the authors briefly discuss the importance, physical nature, effects, and extraction issues of on-chip inductance. Understanding the effects of on-chip inductance in high-speed integrated circuits is crucial to high-performance design     

Analysis of Transmission Lines on Integrated-Circuit Chips

The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the importance of the interconnection problem for the design of high-speed computers. The interconnection delay represents a fundamental boundary which limits the ultimate speed of logic circuits. The transmission-line behavior of interconnections on integrated-circuit chips, especially for subnanosecond applications, is the prime concern of this paper. A lumped circuit model is proposed and justified on physical and experimental grounds. It is shown that interconnections behave like RC transmission lines at low frequencies, with the effect of inductance showing up at midrange and high frequencies. Some simple formulas are included for design use.     

平行光纤互联技术：高性能和低能耗的结合

This paper analyzes the physical potential,computing performance benefit and power consumption of optical interconnects. Compared with electrical interconnections, optical ones show undoubted advantages based on physical factor analysis. At the same time, since the recent developments drive us to think about whether these optical interconnect technologies with higher bandwidth but higher cost are worthy to be deployed, the computing performance comparison is performed. To meet the increasing demand of large-scale parallel or multi-processor computing tasks, an analytic method to evaluate parallel computing performance of interconnect systems is proposed in this paper. Both bandwidth-limit model and full-bandwidth model are under our investigation. Speedup and efficiency are selected to represent the parallel performance of an interconnect system. Deploying the proposed models, we depict the performance gap between the optical and electrically interconnected systems. Another investigation on power consumption of commercial products showed that if the parallel interconnections are deployed, the unit power consumption will be reduced. Therefore, from the analysis of computing influence and power dissipation, we found that parallel optical interconnect is valuable combination of high performance and low energy consumption. Considering the possible data center under construction, huge power could be saved if parallel optical interconnects technologies are used.     

A three-dimensional high-throughput architecture usingthrough-wafer optical interconnect

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

Technology leverage for ultra-low power information systems

Many applications for future generations of logic and memory chips will be requiring highly sophisticated computing functions at low cost. Small form factors, portability, and low cost will require low power operation. While continued scaling of silicon technology to dimensions below quarter micron devices and interconnections appears technically feasible, higher levels of integration and operation at higher speed have been driving the power consumption of logic chips up instead of down. This paper discusses how scaled submicron silicon technology can provide leverage to reduce power, while gaining in throughput for logic chips, and in capacity for memory functions. Strong reductions in voltage supply have to accompany shrinking dimensions. Materials limits such as tunneling currents through ultra-thin silicon-dioxide gate dielectrics and electromigration in minimum pitch interconnections emerge to be key challenges to realize low power 0.1 μm level CMOS circuits. A more than 10× gain in productivity as measured by the energy*delay product can be realized by shrinking from 0.5-0.125 μm CMOS device technology     

新型光接收系统架构：应用于超大容量低成本的短距光互连

大规模数据中心等新兴网络基础设施的部署急需超大容量低成本的短距光互连系统。传统的直调直检系统拥有简单的接收机结构,但只能检测信号的强度信息,这限制了其系统容量的进一步扩展。经典的相干传输系统能够调制解调高阶信号进而实现大容量传输,但收/发端都需要昂贵的窄线宽激光器和高复杂度的数字信号处理,这阻碍了其在短距光互连中的广泛应用。新型的直接检测光接收系统旨在结合直接检测和相干检测两者的优点,弥补二者之间的研究空白。因此,新型的光接收系统架构主要基于自相干检测。介绍了新型单偏振、双偏振、少模光接收系统架构。该类新型的光接收系统不需要本振激光器且能通过直接检测恢复光场信号,实现超大容量低成本的短距光互连。     

Monolithic integration of diffractive lenses with LED-arrays forboard-to-board free space optical interconnect

Since optical interconnections can severely reduce problems associated with electrical interconnect technology (including bandwidth limitations, electromagnetic cross talk, signal delay and EMI aspects), the development of suitable electrooptic components is of crucial importance for implementation of optical interconnects in future computer systems. This paper addresses the design, modeling, fabrication as well as experimental assessment of LED-arrays, with diffractive lenses etched into the rear side of the LED-substrate. The suitability of such optical sources for board-to-board optical interconnections will be demonstrated     

A prototype 3D optically interconnected neural network

We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4×4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 10⁴/cm² seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node