共查询到18条相似文献,搜索用时 78 毫秒
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本文介绍了用原理图输入方法设计一款图象处理ASIC芯片中乘加单元的核心运算部件——32位超前进位加法器,出于速度(时延)和面积折衷优化考虑,它以四位超前进位加法器和四位超前进位产生器为基本设计单元级联而成,因此该电路具有速度和面积的折衷优势。选择原理图输入方法,是考虑到本电路复杂度不高,而原理图输入可控性好,效率高,可靠性强且直观,可以熟悉较底层的结构。文章先给出电路的设计实现,并且是先设计四位超前进位加法器,再提出32位超前进位加法器的设计思想和设计原理,然后再通过测试文件的逻辑验证正确。本设计的所有内容,都将在SUN工作站上Cadence工具Schematic Composer中完成。 相似文献
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随着DSP处理器运算速度的大幅提高,为进一步提高运算速度,各种不同结构的加法器设计相继提出.其中并行前缀加法器以其简单的标准单元和规则的内部连接的结构特点,非常适合VLSI的实现.基于Verilog语言,对快速并行前缀Ling型加法器设计进行RTL级验证,并分析比较不同的验证方法. 相似文献
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子字并行加法器能够有效提高多媒体应用程序的处理性能。基于门延迟模型对加法器原理及性能进行了分析,设计了进位截断和进位消除两种子字并行控制机制。在这两种机制的指导下,实现了多种子字并行加法器,并对它们的性能进行了比较和分析。结果表明进位消除机制相对于进位截断机制需要较短的延时,较少的逻辑门数以及较低的功耗。在各种子字并行加法器中,Kogge-Stone加法器具有最少的延迟时间,RCA加法器具有最少的逻辑门数和最低的功耗。研究结果可以用于指导子字并行加法器的设计与选择。 相似文献
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The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders. 相似文献
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基于可编程器件的加法器结构研究 总被引:1,自引:0,他引:1
加法运算是数字信号处理最基本的运算,随着各种可编程逻辑器件在数字信号处理领域越来越多的应用,高速加法器在可编程器件上的研究应该得到人们的重视。文章根据VirtexTM-E器件的特点,分析了各种常用加法器结构在可编程器件上实现的可行性和将遇到的问题,给出了一种适于可编程器件的行波进位/跳跃进位加法器实现形式。 相似文献
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This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power. 相似文献
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为了提高Smith-Waterman算法处理速度,同时不改变原算法的准确性,本文利用前缀计算方法修改Smith-Waterman算法,并进行OpenMP并行化。在多核机上测试表明,前缀计算的共享并行化使得该局部比对算法的速度得到很大的提高。 相似文献