Noise-tolerant quantum MOS circuits using resonant tunneling devices

Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.     

A Fault-Detection System for Digital Integrated Circuits

A system has been developed for the detection of most commonly occurring faults in digital IC's. Such faults consist of either permanent ("stuck-at") logic levels at input or output terminals, or short-circuits between adjacent terminals in a microcircuit. In the test system to be described both input and output terminals are simultaneously analyzed under quasi-optimum test patterns. The input and output test patterns for each circuit of interest are stored in an average of 330 bits of READ-ONLY memory. The present system is capable of testing the logic operation of CMOS and all families of TTL circuits.     

A Testing Approach for MOS Circuit Using Single-Photon Detectors Under High Magnetic Fields

The MOS circuits must be tested thoroughly for insuring the reliability. A new testing approach for MOS circuits is presented in this paper, which makes use of single-photon detectors and high magnetic fields. If there are faults in the circuit under test, the photon emission from the circuit components is detected by a single-photon detector, the faults are located by the amount of the emitted photons. The following two techniques are proposed in this paper. First, the high magnetic field is applied to the circuit under test, i.e., the circuit is put in high magnetic field environment. To some extent this technique can solve the problem that some faults have poor strengths of emitted photons under general environment. Second, the special circuit input vectors are designed by using binary decision diagrams. The input vectors can make the positions of circuit components to produce signal transitions or switching behaviors, therefore the photon emission strengths of circuit components are enhanced. A lot of experimental results show that the faults in MOS circuits can be tested accurately by the approach proposed in this paper.     

新型8管一位全加器电路设计

通过对已有全加器电路的研究与分析,提出了仅需8个晶体管的新型全加器单元.新电路包括2个3管同或门模块和1个选择器模块.在台积电(TSMC)0.18μm互补氧化物半导体(CMOS)工艺器件参数下经电路模拟程序(HSPICE)进行性能测试,与现有典型的全加器相比,新电路在晶体管数目、功耗和功耗延迟积有较大的优势.     

A two-step methodology for CMOS VLSI reliability improvement: Step one

Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck-at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two-step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre-SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.     

A complete scheme of built-in self-tests (BIST) structure for faultdiagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience     

一种自动体偏置多阈值电压高温 SOI CMOS电路

提出了一种高温OICMOS电路设计方法－－自动体偏置多阈值电压SOICMOS（简称ABB－MT－SOICMOS：Auto-Bulk-BiasedMulti-ThresholdSOICMOS）电路。文中主要讨论了ABB－MT－SOICMOS电路的结构与工作原理,设计与布局等,给出了内部电路电压和电流的模拟结果,并简述了该电路的应用前景。     

基于L-M算法的雷达板级电路快速故障诊断

新型雷达可更换的板级电路很多,为了快速诊断板级电路故障,将一种基于L-M算法的神经网络用于故障诊断;分析了L-M算法BP网络进行雷达板级电路故障诊断的原理;建立了故障诊断样本训练和测试平台;并以实例在该平台上对L-M算法BP网络进行训练和实际诊断,结果表明,该方法诊断准确性高,比其它方法更为快速有效,较好地解决了雷达可更换板级电路的故障诊断问题。     

Design for testability techniques for CMOS combinational gates

The design of easily testable CMOS combinational circuits is discussed. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect a large number of bridging faults. These techniques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (dynamic fully CMOS, DFCMOS), the transistors are controlled by a single input; in the other case (testable fully CMOS, TFCMOS), there is one input for each additional transistor. The test procedure is presented, and it is shown that multiple fault detection can be easily achieved     

High-accuracy circuits for on-chip capacitive ratio testing andsensor readout

This paper presents novel CMOS switched-capacitor circuits for high-accuracy, on-chip capacitive-ratio testing and sensor readout. Using sigma-delta and correlated-double-sampling (CDS) techniques, these circuits provide accurate digitized capacitive-ratio readout. Both single-ended and fully differential circuits are presented. Simulation results show that the resolution can be as fine as 100 aF for 10 pF capacitors. Single-ended circuit and fully-differential circuits were implemented and tested. The measured standard deviation was below 20 aF when 10 pF capacitors were tested     

CMOS circuit testing via time-resolved luminescence measurements and simulations

The continuous trend in modern CMOS technology toward smaller devices and faster clock frequency is challenging the picosecond imaging circuit analysis technique. In this paper we discuss the role of the single-photon avalanche diode with very sharp time resolution in testing CMOS circuits. Thanks to the 30 ps-time resolution, innovative measurements regarding delays and jitter are presented, along with a case study. A compact model of the luminescence is also proposed and used to compare on-chip electrical signals with optical waveforms.     

Low-Power STDR CMOS Sensor for Locating Faults in Aging Aircraft Wiring

A CMOS sensor used to locate intermittent faults on live aircraft wires is presented. A novel architecture was developed to implement the Sequence Time Domain Reflectometry method on a 0.5-mum integrated circuit. The sensor locates short or open circuits on active wires with an accuracy of +/-1 ft when running at a clock speed of 100 MHz. A novel algorithm is proposed that utilizes the shape of the correlation peak to account for sub-bit delay, thus increasing the accuracy of fault location. The power consumed by the microchip is 39.9 mW     

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 10²⁴times10²⁴-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum² and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.     

CMOS adjustable Schmitt triggers

Three adjustable Schmitt triggers for implementation in CMOS technology are presented: two semi-adjustable circuits using only six transistors and one fully adjustable circuit using a total of eight transistors. The most significant features of all three are the hysteresis adjustment, two operation modes as a comparator or Schmitt trigger, very small chip area, and very low static power consumption. The fully adjustable Schmitt trigger has been realized using a 3-μm CMOS technology, and experimental results are presented     

基于动态电路的高速发送端设计

为了降低高速串行接口中发送端的延迟,在研究、分析现有发送端结构的基础上,提出了新的数据跨时钟域传输方法并在实际电路中得到实现。此方法可以大幅降低数据跨时钟域传输时用于异步FIFO的延迟。而且,使用动态电路对高速发送端并串转换电路进行了晶体管级的改进,放松了关键路径的时序要求,使发送端整体电路能运行在更高的频率下。发送端电路使用40nm CMOS工艺实现,实际芯片测试数据表明,使用该电路的发送端可以稳定工作在13Gb/s的速率下。     

A Time-Domain Sub-Micro Watt Temperature Sensor With Digital Set-Point Programming

To realize the on-chip temperature monitoring of VLSI circuits, an accurate time-domain low-power CMOS thermostat based on delay lines is proposed. Contrary to the voltage-domain predecessors, the proposed circuit can benefit from the performance enhancement due to the scaling down of fabrication processes. By replacing R-string voltage division and voltage comparator with delay line time division and time comparator, only little static power is consumed. The power consumption and chip size can be reduced substantially. Without any bipolar transistor, the temperature sensor composed of a delay line is utilized to generate the delay time proportional to the measured temperature. Instead of a conventional voltage/current DAC or an external resistor, a succeeding multiplexer (MUX) along with a reference delay line is used to program the set-point. The test chips with mixed-mode design were fabricated in a TSMC CMOS 0.35-mum 2P4M digital process. The chip area is merely 0.4 mm². The effective resolution is around 0.5degC with a 256-to-1 multiplexer and -40degC ~ 80degC nominal temperature range. The achieved measurement error is within plusmn0.8degC for a total of 20 packaged chips over the temperature operation range of commercial ICs. The power consumption is 0.45 muW per conversion and a measurement rate as high as 1 MHz is feasible when necessary.     

磁通门CMoS接口电路设计

为实现三端式磁通门接口电路的集成．提出一种新颖的包括驱动和检测功能的磁通门CMOS接口电路．驱动电路采用开关网络和负反馈环实现全差分驱动来替代传统的隔离变压器驱动．通过实时平衡驱动电极上的电压信号来抑制电源电压的漂移以及温度变化的影响．检测电路利用驱动信号二倍频为基准的开关相敏解调实现二次谐波提取,同时采用闭环检测．以提高系统线性度．该电路基于0．5IxmCMOS工艺实现．测试结果表明,该微型磁通门磁力计（三端式探头和CMOS接口电路）的灵敏度为30．8μV／nT,非线性度为0．62％,电源电压为10V,功耗为100mW,芯片面积仅为15．54mm2．     

Effect of glitches against masked AES S-box implementation and countermeasure

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.     

Analytical Models for the Performance of von Neumann Multiplexing

As conventional silicon CMOS technology continues to shrink, logic circuits are increasingly subject to errors induced by electrical noise. In addition, device reliability will become a problem, and circuits will be subject to permanent faults. Rather than requiring the circuit to be defect-free, fault-tolerance techniques can be incorporated to allow the continued operation of these devices in the presence of defects. We present an improved model for the reliability of nand multiplexing, a fault-tolerance technique typically requiring large levels of redundancy. It extends previous models to account for dependence between the inputs and derives the distribution of the outputs of each stage when subject to errors. The Markov chain approach used in earlier models is shown to be correct in modeling the effect of multiple stages. Our new model produces more accurate results for moderate levels of redundancy. An example shows the required hardware redundancy is reduced by 50% versus the previous binomial model. In addition, three new types of errors are modeled: the output stuck-at-one, output stuck-at-zero, and input stuck-at-zero faults     

Sparse convolutional autoencoder-based fault location for drive circuits in nuclear reactors

Drive circuit is a critical part of instrumentation and control systems in nuclear reactors, and its performance directly influences the operation of nuclear reactors. However, comparing with the open circuit IGBT faults, soft faults caused by the degradation of electronic components present much slighter fluctuations to the performance of drive circuits. If the two fault modes co-exist, traditional fault diagnosis models are prone to misclassify soft faults as the normal condition. To improve the accuracy of fault diagnosis of drive circuits, it necessitates to accurately locate the faults of drive circuits, while effectively extracting the distinguishable fault features is one of the critical factors for fault location. In this article, a fault location method combining the empirical modal decomposition (EMD) algorithm and sparse convolutional autoencoder (SCAE) is proposed. The EMD algorithm is applied to decompose the three-phase current signals of drive circuits. An SCAE-based feature extractor is constructed to capture high-dimensional and sparse fault feature data with the aid of the powerful feature autonomic extraction capability of deep learning. A deep classifier is designed to locate faults in the driver circuit. A fault simulation model of the drive circuit is developed and the monitor data is collected. The effectiveness of the proposed method is validated via a real case of drive circuit in nuclear reactors.