A 1.9-GHz Direct Conversion Transmitter IC with Low Power On-Chip Frequency Doubler

A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with f of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90° phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90° phase-shifter instead of a voltage-driven 90° phase-shifter. An LO leakage of less than –25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above –15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm×3 mm.     

A 5-GHz frequency-doubling quadrature modulator with a ring-typelocal oscillator

The direct-conversion quadrature modulator described here was developed by using a frequency-doubling circuit technique so that the modulator and the local oscillator can be integrated on a single silicon chip. The local oscillation frequency in the modulator can be reduced to half the carrier frequency, and this enables the integration on a single chip. A three-level mixer with a newly designed symmetrical topology for two local oscillator inputs is used for the frequency doubling, so the image component levels of the modulated signals are low. When the modulator was implemented on a single chip by using Si-bipolar process technology with a cutoff frequency of 40 GHz, the image ratio at a carrier frequency of 5 GHz was less than -34 dBc     

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOStechnology

This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-μm digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW     

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz     

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

A 2-GHz Si-bipolar direct-conversion quadrature modulator with a wide bandwidth is described. It operates at a low supply-voltage of 2 V and features a “current-folded” double-balanced mixer with a two-stacked-transistor configuration, and a tunable RC/CR 90° phase shifter that reduces the amplitude imbalance and the phase error over a wide bandwidth (0.8 to 2 GHz). The modulator is implemented using 18-GHz Si-bipolar technology and dissipates only 68 mW at 2 V. The image ratio at 2 GHz is about -37 dBc, corresponding to a phase error of 1.6°. Moreover, both second-order and third-order products, and local signal leakage are less than -40 dBc     

A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control

This brief presents a new quadrature phase-shift keying (QPSK) modulator for Bluetooth applications with an optimal transaction bandwidth control. The modulator reduces the bandwidth of the modulated carrier by minimizing their transition sharpness. CMOS active transformers are developed and utilized in quadrature oscillator and multiplexer of the modulator to provide comparable phase noise performance without using spiral inductors and transformers. The performance of the modulator is assessed using a 1.6-GHz QPSK base-band modulator implemented in TSMC 0.18-mum 1.8-V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The total transistor area and power consumption of the modulator are 2840 mum² and 30 mW, respectively. The phase noise of the quadrature oscillator is 110 dBc/Hz at 500-kHz frequency offset.     

Design of Broadband Highly Linear IQ Modulator Using a 0.5$mu$m E/D-PHEMT Process for Millimeter-Wave Applications

A broadband highly linear IQ modulator using a 0.5-mum enhancement/depletion-pseudomorphic high-electron mobility transistor process is presented in this letter. An innovative broadside/edge coupler is proposed to apply to the IQ modulator. The chip size is only 1times1 mm², including radio frequency and baseband PADs. The sideband and local oscillation suppressions of the modulator are better than -33 and -15 dBc, respectively. At a carrier frequency of 60 GHz with a 64 quadrature amplitude modulation (QAM) modulation, the modulator demonstrates an error vector magnitude of within 3%, and an adjacent channel power ratio of better than -40 dBc. To the best of the authors' knowledge, this work demonstrates the best modulation quality with a 64 QAM modulation up to 60 GHz among all the reported reflection-type IQ modulators.     

An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively     

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-/spl mu/m SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5/spl deg/. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

Broad-band HBT BPSK and IQ modulator MMICs and millimeter-wave vector signal characterization

Reflection-type binary phase-shift keying and in-phase and quadrature modulator monolithic microwave integrated circuits (MMICs) are reported in this paper. These MMICs are fabricated by 1-/spl mu/m HBT process and evaluated successfully under vector signal characterization. A cold-mode HBT device model with varying bias conditions is proposed, which is suitable for millimeter-wave circuit design and simulation. The analysis and design equations of imbalance effects for the reflection-type modulators are also presented. These MMICs demonstrate measured error vector magnitude of less than 12%, a carrier rejection of better than 15 dB, and an adjacent channel power ratio of better than -21 dBc from 50 to 110 GHz.     

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V     

Harmonic-suppressed quadrature-input frequency divider for OFDM systems

A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed.The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals.Compared with conventional dividers,the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence.Moreover,the third harmonic is effectively suppressed by employing a double degeneration technique. The desig n is fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V.While locked at 8.5 GHz,the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset.The circuit achieves a locking range of 15%while consuming a total current of 4.5 mA.     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.