Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

低噪声CMOS运算放大器的优化设计方法

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.     

Eliminating complex conjugate poles in two-stage operational amplifiers with current buffer Miller compensation

This paper describes conditions and simple circuit modifications that eliminate undesired complex conjugate poles in two-stage operational amplifiers that are based on current buffer Miller compensation. The complex conjugate poles have been the main problem of this frequency compensation topology since its first introduction more than 30 years ago. It is shown that a resistor added between the second stage and the amplifier output creates a zero that improves stability and reduces the circuit to a second-order system. This greatly simplifies the design of an otherwise complex topology and at the same time retains the valued benefits of current buffer based frequency compensation. In addition, for the case where a short channel transistor is used for the current buffer, conditions that create sufficient phase margin for the inner loop of the amplifier without the nulling resistor are formulated.     

Design approach for fast-settling two-stage amplifiers employing current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach defines a systematic procedure to optimize the amplifier time response, allowing the required speed performances to be achieved without both power wasting and blind efforts for time-consuming trial-and-error design processes. To demonstrate the effectiveness of the methodology, a design example in a commercial 0.35 μm CMOS technology is presented. As shown by circuit and statistical simulations, the proposed strategy proves to be very useful to develop fast-settling operational amplifiers for typical discrete-time applications, such as switched-capacitor filters and ΣΔ analog-to-digital converters.     

Current gain high-frequency CMOS operational amplifiers

The performance of high unity gain-bandwidth current gain-based CMOS operational amplifiers fabricated in a 1.5-/spl mu/m CMOS digital process is discussed. High unity-gain bandwidth was achieved by using short-channel MOS transistors operating in the current gain mode. Stacked current mirrors have been utilized as current gain stages to minimize the effects of the channel-length modulation in short-channel MOS transistors. Open-circuit gain of 60 to 70 dB, a unity-gain bandwidth of 70 to 100 MHz, and slew-rate of 200 V//spl mu/s were demonstrated at a DC power dissipation of 1-2 mW.     

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

A compact rail-to-rail output stage for CMOS operational amplifiers

This paper presents a CMOS output stage devised for driving heavy resistive loads. An operational amplifier of this type has been fabricated in a 3 μm double-polysilicon CMOS technology. With a supply voltage of ∓5 V and load of 470 Ω, the amplifier has a ∓4.6-V output swing and features a 60 mA short-circuit output current. Although simple, the proposed configuration enables the output transistors to be driven efficiently     

An improved frequency compensation technique for CMOS operational amplifiers

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.     

Rail-to-rail super class AB CMOS operational amplifiers

Novel class AB single-stage operational amplifiers are presented. They feature rail-to-rail operation owing to the use of floating-gate input transistors. Initial charge of the floating gates is removed during fabrication, without any post-processing. The amplifiers are fast, simple, and able to operate at low supply voltages. They are highly power efficient owing to the enhanced (super) class AB operation based on adaptive biasing and local common-mode feedback. A 0.5 /spl mu/m CMOS implementation shows rail-to-rail operation with slew rates of about 40 V//spl mu/s for a load of 80 pF and 144 /spl mu/W of quiescent power consumption.     

A family of high-swing CMOS operational amplifiers

A family of high-swing CMOS operational amplifiers has been developed to maximize the available dynamic range with low supply voltages. Complementary differential pairs are used to achieve an almost rail-to-rail input common-mode voltage range. High linearity is obtained by summing currents so that the small-signal differential-mode voltage gain is constant over the entire input common-mode range. With a 5.0-V power supply, the total harmonic distortion is typically only 1% in a unity-gain configuration with a 4.5-V_p-p signal. The measured DC offset voltages versus input common-mode range track between the conventional and high-swing versions. These measurements suggest that the commonly feared crossover distortion may not be a problem when the current summation high-swing topology is used. The measured step response characteristics were excellent and exhibited no signs of phase mismatch crossover distortion for high-frequency signals     

Current mode biquadratic filter realizations employing operational amplifiers

New circuit configurations for realizing current mode biquadratic filter sections using operational amplifiers are presented. Each circuit uses a single operational amplifier and seven passive elements at most. The merits and demerits of the proposed realizations are discussed.     

Linear resistance-to-frequency conversion employing integrated circuit operational amplifiers

A simple approach is presented for synthesizing linear R/f converters which may be useful in measurement systems employing restive transducers. Four R/f converters are derived each of which employs only three integrated circuit operational amplifiers along with a few RC components. Experimental results are found to be in agreement with the theoretical values.     

Novel input stages for current feedback operational amplifiers

This paper considers the trade-offs involved in the design of six new input stages intended to improve the performance of a current feedback operational amplifier (CFOA), over that possible using an established input circuit configuration, with respect to three major characteristics, viz, common mode rejection ratio (CMRR), offset voltage and slew-rate.     

Design techniques for monolithic operational amplifiers

The characteristics of recently developed integrated-circuit components are reviewed and some new devices are described. Their impact on the design of monolithic operational amplifiers is also discussed. Emphasis is placed on realizing particularly good dc characteristics-especially low input current. However, techniques for obtaining higher operating speeds are also covered.     

Design of SOI CMOS operational amplifiers for applications up to300°C

Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300°C. The dependence of these parameters on temperature is first described. A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300°C for applications such as micropower (below 4 μW at 1.2 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz. Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described. The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps     

Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.     

Applications of the current feedback operational amplifiers

The current feedback operational amplifiers (CFOAs) are receiving increasing attention as basic building blocks in analog circuit design. This paper gives an overview of the applications of the CFOAs, in particular several new circuits employing the CFOA as the active element are given. These circuits include differential voltage amplifiers, differential integrators, nonideal and ideal inductors, frequency dependent negative resistors and filters. The advantages of using the CFOAs in realizing low sensitivity universal filters with grounded elements will be demonstrated by several new circuits suitable for VLSI implementation. PSPICE simulations using the AD844-CFOA which indicate the frequency limitations of some of the proposed circuits are included.     

CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage

Two 3.3-V operational amplifiers with constant-g _m rail-to-rail input stage and rail-to-rail output stage are presented. The constant transconductance (g _m ) ensures a constant unity-gain frequency within the whole commonmode input range. Two new methods to control theg _m are introduced. Both operational amplifiers use the same rail-to-rail output stage. The operational amplifiers have been integrated in a CMOS semicustom process with transistor lengths of 10µm. The common-mode input voltage swing extends beyond the positive supply rail by 400 mV and beyond the negative supply rail by 200 mV. The output voltage is able to reach within 130 mV of the supply rails. The output current of the operational amplifiers is 2 mA and the voltage gain is 85 dB. The unity-gain frquency is 165 kHz, which is mainly limited by the relatively long transistor lengths of 10µm. In another process with channel lengths of 2µm, simulation results showed that a unity-gain frequency of 4 MHz can easily be obtained.