CMOS射频集成电路的研究进展

近年来，射频集成电路(RFIC)的应用和研究得到了飞速的发展，CMOS射频IC的研究更是成为该领域的研究重点和热点。文章对CMOS技术在射频和微波领域的应用进行了详细的探讨，着重介绍了当前射频通讯中常用的收发机结构及其存在的问题和解决方案；分析了射频收发机前端关键电路模块低噪声放大器(LNA)、混频器(Mixer)、压控振荡器(VCO)、功率放大器(PA)和射频关键无源元件的最新研究进展；展望了CMOS技术在射频领域的发展前景。     

一种单芯片无线收发系统设计

为了使无线收发系统能方便地应用于无线传感器网络、蓝牙技术与无限局域网（WLAN）等领域,采用了片上系统设计方法,将无线收发系统设计在一块单芯片上,使其最小化。给出了单芯片无线电的基本结构及电路实现的若干组成部分（混频器,低噪音放大器,功率放大器等）的解决方案。电路具有体积小,低功耗,成本低,可靠性高的特点。     

A novel low-power transceiver topology for noncontact vital sign detection including the power management technique

In this paper, power management technique utilized in the direct down-conversion non-quadrature transceiver is presented for the low-power application of vital sign detection. The simultaneous switching noise (SSN) and overshoot and undershoot of the transient waveform distortion resulting from a pulse signal will give rise to interference with a vital sign signal. The pulse width, rise/fall time, and period of pulse bias are analyzed to mitigate the interference in this investigation. Significant issues about direct-current (DC) offset and noise confronted by the presented technique are addressed based on mathematical analysis. In radio-frequency (RF) transceiver architecture including power amplifier (PA), low-noise amplifier (LNA), and mixer, the current-reused (CRU) topology is utilized to achieve low DC power consumption. The post-layout simulation results exhibit that power consumption of the transceiver using the optimized pulse bias is reduced to 40% of the power consumption for transceiver applying the DC bias. In addition, DC offset and null detection point can be alleviated by tunable phase shifter.     

A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas

In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi     

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.     

UWB radio module design for wireless sensor networks

In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 μm CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SoP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight’s helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than ?10 dB over the UWB band.     

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

基于Verilog-AMS的VCO噪声建模

压控振荡器(VCO)是锁相环(PLL)的关键部件,目前多数研究都着重于VCO的电路级设计。采用Verilog-AMS语言对VCO进行行为建模,同时加入噪声模型,行为级设计中体现噪声。对比有噪声和无噪声的VCO行为模型,利用Cadence Spectre仿真引擎对2个模型进行了验证,将内嵌VCO行为模型的PLL系统与电路级PLL系统做了对比分析,结论为添加噪声的VCO行为模型更准确,更接近晶体管级电路,对仿真的速度与精度做了较好的折中。     

A 200-MHz sub-mA RF front end for wireless hearing aid applications

A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-μm BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g_m of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz     

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

RF transceiver and transmission line behavioral modeling in VHDL-AMS for wired RFNoC

Despite the exceptional progress of MPSoC architectures, on chip communication networks remain a lock for the evolution of their performances due to the power consumption and the delay in data carrying. In this context, the wired radio frequency (RF) network on chip (RFNoC) has emerged. In this paper, we developed a library of RF component models in VHDL-AMS for time domain simulation. This library includes mainly the transmission line (TL) and the RF transceiver components such as the low noise amplifier (LNA), the mixer and the local oscillator (LO). The models consider the conventional parameters describing their performances including the non-linearities, the noise and the bandwidth of the LNA and the mixer. Leakages between ports are also considered for the mixer. The LO model considers the traditional parameters, more importantly its phase noise. The originality of the TL model is the modeling of the skin effect on a wide frequency range for time domain simulations. All the models are validated. Global simulations are performed to demonstrate the interest to accurately model the components of the RFNoC. The developed library is used here for wired RFNoC, however it can be used for all other wired and wireless RF communication system.     

Design of wide-band CMOS VCO for multiband wireless LAN applications

In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.     

一款130～140GHz MMIC低噪声放大器

基于90 nm栅长的InP高电子迁移率晶体管(HEMT)工艺,研制了一款工作于130 ～140 GHz的MMIC低噪声放大器(LNA).该款放大器采用三级级联的双电源拓扑结构,第一级电路在确保较低的输入回波损耗的同时优化了放大器的噪声,后两级则采用最大增益的匹配方式,保证了放大器具有良好的增益平坦度和较小的输出回波损耗.在片测试结果表明,在栅、漏极偏置电压分别为-0.25 V和3V的工作条件下,该放大器在130～ 140 GHz工作频带内噪声系数小于6.5 dB,增益为18 dB±1.5 dB,输入电压驻波比小于2:1,输出电压驻波比小于3:1.芯片面积为1.70 mm×1.10 mm.该低噪声放大器有望应用于D波段的收发系统中.     

一种用于Bluetooth发接器的倍频式VCO

介绍了一种适用于 Bluetooth发接器的 ,可以单片集成的倍频式压控振荡器 ( VCO)。这种 VCO由两部分组成 ,主 VCO的振荡频率是所需本振频率的一半 ,然后采用“注入锁频”原理对主 VCO的振荡频率进行倍频以产生本振信号。主 VCO和倍频电路都使用了片上集成螺旋电感 ,调谐用的变容元件使用 PMOS晶体管实现。经过版图设计和后仿真 ,在 TSMC0 .35 μm数字 COMS工艺 ,3.3V电源电压下 ,该 VCO在 2 .4GHz中心频率附近可以达到的相位噪声指标为 -1 2 5 d Bc/Hz( 60 0 k Hz) ,在输出摆幅为 60 0 m Vp- p时 ,功耗为 2 2 m W。     

QoS evaluation of energy-efficient ML-MAC protocol for wireless sensor networks

Power management is an important issue in wireless sensor networks (WSNs) because wireless sensor nodes are usually battery powered, and an efficient use of the available battery power becomes an important concern specially for those applications where the system is expected to operate for long durations. This necessity for energy efficient operation of a WSN has prompted the development of new protocols in all layers of the communication stack. If the radio transceiver is the most power consuming component of a typical sensor node, large gains can be achieved at the link layer where the medium access control (MAC) protocol controls the usage of the radio transceiver unit.     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.