The low light level potential of a CCD imaging array

Some limitations to the operation of a CCD TV camera sensor at low light levels are discussed. Transfer inefficiency with small charge packets is analyzed theoretically, and the prediction made that with good processing this should not be a serious problem. The principal limitation is seen to be the output amplifier, and a new low-noise output detector, the "floating surface detector," is described in detail. At -50°C it yields a noise equivalent signal of 16 electrons and a dynamic range of 85 dB over a 1-MHz video bandwidth.     

A 2-million-pixel CCD image sensor overlaid with an amorphoussilicon photoconversion layer

A highly sensitive 2-million-pixel high-definition charge-coupled device (CCD) image sensor was developed that features an overlaid amorphous silicon photoconversion layer on an interline transfer-type CCD scanner. The device is adapted to the 16:9 aspect ratio. 1125 scanning lines and 2:1 interlace high-definition TV system. A dual-channel horizontal CCD register is used to reduce the operating frequency to one half of the 74.25-MHz readout frequency. A horizontal period signal storage memory (1H line memory) is provided between the vertical CCD register and the horizontal CCD register to provide the signal distribution from the vertical CCD to the horizontal CCD register during the 3.77-μs short horizontal blanking interval. This device realized a 1000 TV line horizontal limiting resolution 210 nA/1x high sensitivity. Total random noise was found to be 52 electrons RMS and a 72-dB dynamic range was achieved     

Novel p-JFET embedded in silicon radiation detectors that avoidspreamplifier feedback resistor

The paper describes the design and the performance of an original p-channel JFET embedded in the collecting anode of a silicon radiation detector. The choice of a p-channel transistor, whose gate-to-channel junction is forward biased by the leakage current from the detector, avoids the preamplifier feedback resistor and performs a continuous dc reset of the collected charge. The reported design, fully compatible with the detector fabrication, makes the operation of the detector extremely simple, ensures the best charge collection capability and leads to improved charge resolution. The first detector produced with this type of transistor has a resolution of 27 electrons rms in the measurement of the collected charge at room temperature for a pixel active area of about 0.1 mm², and of 22 electrons rms at T=210 K     

结型场效应晶体管放大器的噪声

本文通过分析结型场效应管(JFET)放大器内部不同的噪声源，首次导出了场效应管放大器在较宽频率范围内的等效输入噪声电压表达式，估算了当信号源阻抗为容性时JFET放大器的总噪声，为场效应管电路低噪声优化设计提供有力的工具。     

Application of Correlated Double Sampling in Space TDICCD Camera

As a sampling technique for CCD output video signal, the correlated double sampling (CDS) technique is described as well as the filtering effects of the CDS technique on the output noise of CCD including the reset noise of CCD, the white noise of output amplifier and 1/f noise. From real application of CDS device TH7982A, it is concluded that the output signal-to-noise ratio of 50 dB for CCD signal can be obtained.     

A CCD video delay line with charge-integrating amplifier

The authors describe a charge coupled device (CCD) sense amplifier in a video delay line which overcomes the major limitations of conventional floating diffusion amplifier (FDA) technology, such as limited output voltage and operating temperature range. These advances are implemented with a switched-capacitor integrator (SCI) using an op amp with a newly developed output stage in a CMOS-CCD process. This circuit is effected within the constraints of 5-V operation by using negative pulses to reach the low channel potential of the CCD in the pinning region in the final gate of the CCD. The chip operates with 14.3-MHz clock and 5-V power supply, and can process a 1.0-V_p-p signal voltage under 1% distortion, and under 4% gain variation from -20 to 70°C     

一种兼顾速度和功率损耗的硅探测器模拟前端电路设计

提出了一种兼顾速度和功率损耗的增益可调模拟前端电路,适用于硅探测器。该电路主要由快速电荷灵敏放大器、整形器以及可调节主要参数的控制系统组成。其中快速电荷灵敏放大器由低噪音场效晶体管（JFET）和电流反馈运算放大器构成,以确保较高频率和较短上升时间。整形器为五阶复数滤波器,能够提供较高的对称脉冲。通过实验验证了其可行性,在电容小于100 pF的范围内,实现了6种可调增益且兼顾了速度和功率损耗,电荷灵敏放大器上升时间为12ns,功率损耗为96mW。当探测器电容为40 pF时,等效噪音电荷（ENC）均值为180e-。     

8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 e_rms ^- by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 e_rms ^-. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 e_rms ^-.     

Low voltage CCD image sensor with optimized reset operation

A charge coupled device (CCD) image sensor operating with 3.0 V-reset has been developed using a charge injection to the gate dielectrics of a MOS structure. A DC bias generating circuit was added to the reset structure, which sets reference voltage and holds the signal charge to be detected. The generated Dc bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 to 5.5 V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with 492(H)×510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

Characteristics of a semiconductor laser pumped brillouin amplifier with electronically controlled bandwidth

We demonstrate the operation of a semiconductor laser pumped fiber Brillouin amplifier. An optical gain of 5.5 dB/mW of pump power is obtained. The 15-MHz intrinsic bandwidth of the amplifier was extended more than one order of magnitude by adding frequency modulation to the pump laser. Bit-error-rate receiver sensitivity measurements with an in-line Brillouin amplifier demonstrate a 16-dB improvement in the system gain at 10 Mbit/s and a 8.5-dB improvement at 90 Mbit/s. Noise calculations show that the amplifier has an excess noise factor of 50-500 depending on the amplifier length and pump power.     

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise     

Analysis of the photosite reset in FGA image sensors

An analysis of the photosite reset mechanism in floating gate array image sensors is presented. The photosite elements in these devices consist of a JFET transistor with the gate capacitively coupled to an address line. The addressed cell is reset by forward biasing the gate-drain junction. During evaluation of the first prototype samples it was found that this reset method has some disadvantages for the device dynamic range and the cell-to-cell signal interference. To eliminate these problems, a method of resetting the photocell using the source-gate junction has been developed and experimentally tested. An analysis of the reset method in the steady-state and transient modes of operation is presented as well as an analysis of noise. The results are used to explain the observation of an image lag which has been detected in these sensors and to calculate the photosite sensitivity which is related to the photosite noise floor. It is shown that the introduction of a small amount of bias charge into the photosite improves the image lag characteristic; however, an ideal solution of this problem is not described     

Theoretical analysis and optimization of CDS signal processingmethod for CCD image sensors

The correlated double sampling (CDS) signal processing method used in processing of video signals from CCD image sensors is theoretically analyzed. The CDS signal processing is frequency used to remove noise, which is generated by the reset operation of the floating diffusion charge detection node, from the signal. The derived formulas for the noise power spectral density provide an invaluable insight into the choice of the circuit parameters affecting the noise spectrum. The obtained results are useful for determining the optimum cutoff frequency of the low-pass filter which precedes the sample-and-hold circuit and for finding the optimum size of the input transistor in the first amplifier stage. Once the optimum parameters are determined it is possible to find the minimum electron equivalent noise and the maximum signal-to-noise ratio achievable with this signal processing method. The validity of the derived theoretical results is confirmed by making comparisons with the experimental data     

256×256 hybrid HgCdTe infrared focal plane arrays

Hybrid HgCdTe 256×256 focal plane arrays have been developed to meet the sensitivity, resolution, and field-of-view requirements of high-performance medium-wavelength infrared (MWIR) imaging systems. The detector arrays for these hybrids are fabricated on substrates that reduce or eliminate the thermal expansion mismatch to the silicon readout circuit. The readouts are foundry-processed CMOS switched-FET circuits that have charge capacities greater than 10⁷ electrons and a single video output capable of 20-MHz data rates. The high quantum efficiency, tunable absorption wavelength, and broad operating temperature range of these large HgCdTe staring focal plane arrays give them significant advantages over competing sensors. The mature Producible Alternative to CdTe for Epitaxy-1 (PACE-1) technology, using sapphire detector substrates, has demonstrated 256×256 MWIR arrays with mean laboratory noise equivalent temperature difference (NETD) of 9 mK for a 4.9-μm cutoff wavelength, 40-μm pixel size, and 80-K operating temperature. RMS detector response nonuniformities are less than 4%, and pixel yields are greater than 99%. The newly developed PACE-3 process uses silicon for the detector substrate to eliminate completely the thermal mismatch with the silicon readout circuit. It has the potential for similar performance in even larger array sizes. A 640×480 hybrid array is under development     

Random noise generation mechanism for a CCD imager with anincomplete transfer-type storage diode

A random noise for a CCD imager with an incomplete transfer-type storage diode is theoretically and experimentally discussed. The theoretical result based on the Fermi-Dirac distribution function is in good agreement with the well known experimental result as a “kTC” noise, which is equal to the square root of kTC/2. It is also shown that the random noise in the storage diode is dependent on the amount of the signal charge, and can be reduced for the small signal charge. Moreover, a small signal reset operation (SSR operation) is newly proposed to suppress the capacitive-image-lag and larger random noise. The reproduced image with the high signal-to-noise (S/N) ratio is obtained for a STACK-CCD imager with the small signal reset operation     

Monolithic integration of fully ion-implanted lateral GaInAs pin detector/InP JFET amplifier for 1.3-1.55 mu m optical receivers

An optical receiver front-end consisting of a lateral interdigitated GaInAs pin detector integrated with an InP JFET amplifier has been fabricated. This lateral detector structure simplifies the GaInAs material growth requirement to a single layer and provides low capacitance. A quasiplanar approach has been developed in conjunction with a two-level metallisation interconnect scheme. An optical sensitivity of -29 dBm was measured at 560 Mbit/s and 1.3 mu m wavelength.<>     

Low-noise and high-speed charge detection in high-resolution CCDimage sensors

This paper analyzes problems associated with low-noise and high-speed charge detection encountered in high-resolution image sensors. It is found that the conventional Floating Diffusion (FD) charge detection concept is inferior to the previously studied, but not frequently utilized, Floating Gate (FG) approach. A new output charge detection well reset technique and an improved biasing method allowed the design of the FG charge detection amplifier with a comparable conversion gain to FD structures but with much better noise performance at the data rates up to 40 MHz. The theoretical analysis of the FG amplifier performance, including the Correlated Pixel Clamp signal processing method, is confirmed by measurements performed on a high-resolution 1000×1000 pixel Frame Transfer CCD image sensor built using an Advanced Virtual Phase Technology. The described details of the sensor design include: (1) the over all device architecture, (2) the pixel cross section with the cross section of the lateral overflow drain antiblooming structure, (3) the dual serial register with a single output amplifier, and (4) the resistive gate reset structure for the output charge detection well. The developed image sensor does not need the conventional Correlated Double Sampling (CDS) circuit for the signal processing, since the FG detection node is sensing charge nondestructively without generation of kTC noise. The described progress in the FG charge detection approach thus opens up a possibility for future designs of distributed FG amplifiers that can theoretically reach the ultimate low-noise performance at virtually any clocking frequency     

A dual-phase-controlled dynamic latched amplifier for high-speedand low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-μm technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier     

Partition noise in CCD signal detection

Reset noise in CCD signal charge detection is analyzed experimentally and theoretically. From a reset noise measurement experiment, it has been inferred that reset noise consists of two parts: the sensing capacitance (Cs) dependent part and the effective reset channel length (L) dependent part. Conventional reset noise theory, where the Johnson noise in the reset MOS channel was regarded as the only noise source, agrees with the Csdependent part of measured reset noise. However, it cannot explain the L dependent part. To explain theLdependence, the authors propose "partition noise" caused by carrier partition in the reset MOS channel. Partition noise is analyzed by the unique technique of solving the one-dimensional diffusion equation. As a result, a reset channel capacitance dependent characteristic for partition noise has been derived, which agrees with theLdependent part for measured reset noise. Consequently, in addition to Johnson noise, partition noise is found to be a noise source in CCD signal detection.     

A CCD image sensor with 768 × 490 pixels

A ⅔-in 768(H) × 490(V) element interline CCD image sensor has been successfully developed. The device adopts a vertical overflow drain principle, a buried,channel amplifier, three-level polysilicon technology, and 1.5-µm-rule fine-pattern process. The device operates with an NTSC format. The 560 TV lines limiting resolution is obtained in the horizontal direction. No significant loss in transfer efficiency is observed in the horizontal register, even at the 14.32 MHz clock rate. Optimal photosensitivity spectrum response is obtained and the peak response appears at 550 nm. The noise equivalent signal is reduced to 48 electrons, using correlated double sampling. Then, the dynamic range reaches 68 dB. The correlated double sampling, combined with buried-channel amplifier technology is found to be also effective for great reduction in horizontal line noise.