Design concept for a low-noise CCD image sensor based on subjectiveevaluation

To achieve a high-performance image sensor for a broadcast TV camera, several studies of the noise characteristics of a CCD image sensor are described. The noise perception limit and the dependence of random noise and fixed pattern noise (FPN) on signal charge in a CCD imager were measured to obtain a correlation between measured noise and subjective noise. A method has been devised to measure FPN and random noise separately. Using this method, it has been confirmed that noise can be reduced to less than the perception limit using new noise-suppression techniques     

一种低差分输出不匹配度的单转差分低噪声放大器

本文设计了一种应用于GPS接收机的单端输入差分输出低噪声放大器。我们提出了一种利用变压器或中心抽头差分电感中的电感耦合来降低差分输出不匹配度的方法。文中对降低不匹配度的原理进行了分析,并且讨论了如何选择电感尺寸。本文的LNA带ESD保护,使用TSMC 0.18um工艺实现,并且封装后在PCB上进行测试。LNA工作在1.575GHz,电压增益为24.6dB, 噪声系数为3.2dB,差分输出增益不匹配度小于0.2dB,相位不匹配度小于2度,LNA工作电压为1.8V,消耗5.2mA电流。     

A 1920(H)×1035(V) pixel high-definition CCD image sensor

A 1920(H)×1035(V)-pixel high-definition CCD (charge-coupled-device) image sensor compatible with an 1125-scanning-lines and 16:9 aspect-ratio television system is described. The device basically uses an interline scheme with a vertical overflow drain. To maintain 74.25-MHz ultrahigh-data-rate operation, the device adopts a dual-channel configuration for the horizontal CCD (H-CCD) register. To accomplish both vertical signal charge transfer in the vertical CCD (V-CCD) register and signal charge distribution from the V-CCD registers into the dual-channel horizontal CCD registers simultaneously within a 3.77-μs short horizontal blanking period, a one-horizontal-period signal storage memory electrode and optical black memory are introduced. Bipolar buffer transistor chips are hybridized in the same package as the device, so as to reduce parasitic capacitance at CCD output terminals and maintain a wide-bandwidth operation. The device operates successfully and 1000-TV-line limiting resolution was obtained for both vertical and horizontal directions. Total random noise was evaluated to be 41 electrons. Dynamic range reached 66 dB. Signal-to-noise ratio for a black/white (B/W) camera was 51.5 dB under F4.0 and 2000-lux illumination conditions     

CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

Ultra-wideband SiGe low-noise amplifier

A low-noise amplifier (LNA) for ultra-wideband (UWB) is presented. The LNA, consisting of two gain stages in multiple feedback loops, achieves a flat power gain of a nominal 20 dB and a noise figure of 2.8-4.7 dB over the 3.1-10.6 GHz UWB band. Implemented in a 0.25 /spl mu/m SiGe BiCMOS process, the amplifier occupies 0.34 mm/sup 2/ and draws 11 mA from a 2.7 V supply.     

High-dynamic-range low-noise microwave amplifier

The operation of a high-dynamic-range parametric amplifier is described. The varactor is a GaAs p?n junction with an n type layer suitable for operation as a K band transferred-electron oscillator (t.e.o.). A dynamic range of approximately 177 dB/Hz and a noise figure of less than 2 dB were measured at C band. The tests were made to show the feasibility of high-dynamic-range low-noise microwave amplification for radar-receiver applications, and to establish the feasibility of high-performance monolithic multifunction chips from the material standpoint.     

高帧速CCD摄像器件的设计

设计了光敏元尺寸１８μｍ×１８μｍ５１２（Ｈ）×５１２（Ｖ）光纤面板耦合ＣＣＤ高帧速摄像器件,帧速为５００帧／ｓ。详细讨论器件多相加压（ＭＰＰ）和常规工作模式的设计,给出了器件设计性能参数。该器件采用２μｍ,双层多晶硅和双层金属工艺制作。     

线阵CCD图像传感器驱动电路的设计

随着CCD性能的不断提高,CCD技术在军、民用领域都得到了广泛的应用.介绍了TCD1501C线阵CCD的驱动电路设计,详细介绍了用VHDL完成的CCD图像传感器驱动时序设计和视频输出差分信号驱动电路的设计.     

An infrared-bi-color Schottky-barrier CCD image sensor for precisethermal images

An infrared-bi-color image sensor was developed with a barrier height controlled Schottky-barrier photo diode array for precise temperature images. Low and high barrier height diode pixels are arranged vertically next to one another using a selective area ion implantation technique. Conventional monochrome infrared image sensors frequently give wrong temperature images due to an unreasonable emissivity assumption. The infrared-bi-color image sensor can obtain the temperature image precisely with regard to the emissivity of the object     

A low-noise BiCMOS amplifier channel for telecommunications

A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances.     

A meander channel CCD linear image sensor

A new type of 1024-element linear image sensor has been developed using a CCD with a meander channel (MCCD). Its simple electrode pattern with no contact windows for clocking promises high yield in the production.     

CCD image sensor with compensated reset operation

A low voltage charge coupled device (CCD) image sensor has been developed by adjusting the electron potential barrier in the electron sensing structure. A charge injection to the gate dielectrics of a MOS transistor was utilized to optimize the electron potential level in the output structure. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 V to 5.5 V, which is suitable for compensating the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole–Frenkel conduction and Fowler–Nordheim conduction. A CCD image sensor with 492(H) × 510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

CCD图像传感器的高分辨率技术

评价了 Ｃ Ｃ Ｄ 图像传感器与电子束摄像管的性能。分析了高分辨率 Ｃ Ｃ Ｄ 像感器的技术难点。阐述了解决这些问题的技术措施：双 Ｈ－ Ｃ Ｃ Ｄ 移位寄存器、 Ｓ Ｒ Ｄ 法、 Ｃ Ｃ Ｓ 法及微透镜技术等。给出了三种新器件的技术指标,并与常规方法构成的器件进行了比较     

Performance improvement of CCD image sensor arrays

In conventional arrays, charges are read out from photodiodes through vertically placed charge-coupled registers. In an array presented here, reading out is performed through vertical diffusion lines. As shown, such an array is more sensitive, since the photodiodes occupy a larger space. Also, this array shows a reduced level of cross-coupling, because extra charges leave the photodiodes, and a reduced level of intrinsic back-ground, because charges generated exterior to the photodiodes are removed.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

A low-noise NMOS operational amplifier

NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW.     

X波段低噪声放大器的设计

为了实现X波段的低噪声放大器,介绍了按最小噪声系数设计,采用两级级联,利用Eudyna公司的HEMT晶体管设计制作的低噪声放大器。通过专用微波电路设计软件(AWR),对该电路的稳定系数、功率增益、噪声系数、驻波比、匹配网络等进行了仿真分析。根据分析结果制作的X波段LNA取得了如下指标:在9.5～10.5 GHz频带内,功率增益大于22 dB,噪声系数小于1.5 dB,输入输出驻波小于1.7。     

A low-noise CMOS instrumentation amplifier for thermoelectricinfrared detectors

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-μm single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV/√Hz. The typical residual input offset is 1.5 μV. The amplifier power consumption is 1.3 mW     

Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design

In this paper, we present a systematic synthesis methodology for fully integrated narrow-band CMOS low-noise amplifiers (LNAs) in high-performance system-on-chip (SoC) designs. The methodology is based on deterministic gradient-based numerical nonlinear optimization and the normal boundary intersection (NBI) method for Pareto optimization. We simultaneously optimize transistor widths, bias voltages, and input and output matching network passive components, which yields integrated inductor values that are more than one order of magnitude less than those generated by several existing equation-based LNA design techniques. By generating significantly smaller inductor values, we enable the SoC integration of the complete LNA. When the synthesized LNAs are characterized using circuit-level simulation, our methodology yields up to 35% and 58% improvement in noise figure and gain, respectively.     

Interline CCD image sensor with an antiblooming structure

A ⅔-in 384 (H) × 490 (V) element interline CCD image sensor with a new antiblooming structure was developed. Blooming was suppressed without sacrificing photosensitivity and dynamic range by means of a vertical overflow drain positioned under (rather than beside) a photodiode. For 10-percent vertical height illumination the smear signal was reduced to 0.05 percent of the illumination signal. Well-balanced performance, namely, large dynamic range (72 dB), low random noise (65 rms noise electrons per charge packet), high-contrast transfer functions for horizontal and vertical directions, and a spectral response similar to the luminous efficiency curve were obtained under moderate operating conditions.