Intrinsic Parameter Fluctuations in Conventional MOSFETs at the Scaling Limit: A Statistical Study

A statistical study of intrinsic parameter fluctuations due to discrete random dopants in well scaled conventional MOSFETs is presented, using 3D simulations with quantum corrections to resolve the effects of individual dopants. The scaled devices are based on a realistic 35 nm gate length MOSFET. A significant increase in the parameter fluctuations in the devices scaled below 20 nm gate lengths have been observed.     

Random dopant related variability in the 30 nm gate length In<Subscript>0.75</Subscript>Ga<Subscript>0.25</Subscript>As implant free MOSFET

Implant free MOSFETs take advantage of the high mobility in III–V materials to allow operation at very high speed and low power. However, as with conventional silicon devices, they will be susceptible to intrinsic parameter fluctuations due to random discrete doping. In this paper, we investigate the impact of random discrete dopants induced fluctuations in the δ-doping layer on the threshold voltage of the 30 nm gate length implant free III–V MOSFET.     

Hybrid MOSFET/driver for ultra-fast switching

The ultra-fast switching of power MOSFETs, in about 1 ns, is very challenging. This is largely due to the parasitic inductance that is intrinsic to commercial packages used for both MOSFETs and drivers. Parasitic gate and source inductance not only limit the voltage rise time on the MOSFET internal gate structure but can also cause the gate voltage to oscillate. This paper describes a hybrid approach that substantially reduces the parasitic inductance between the driver and MOSFET gate, as well as between the MOSFET source and its external connection. A flip-chip assembly is used to directly attach a die-form power MOSFET and driver on a PCB. The parasitic inductances are significantly reduced by eliminating bond wires and minimizing lead length. The experimental results demonstrate ultra-fast switching of the power MOSFET with excellent control of the gate-source voltage.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

SiC MOSFET驱动电路及实验分析

根据SiC MOSFET开关特性,设计了一种SiC MOSFET的驱动电路,在此基础上采用双脉冲测试方法,对SiC MOSFET的开关时间、开关损耗等进行了实验测量,分析了不同驱动电阻对SiC MOSFET开关时间、开关损耗等的影响。     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices

As MOSFETs are scaled to sub 100 nm dimensions, quantum mechanical confinement in the direction normal to the silicon dioxide interface and tunnelling (through the gate oxide, band-to-band and from source-to-drain) start to strongly affect their characteristics. Recently it has been demonstrated that first order quantum corrections can be successfully introduced in self-consistent drift diffusion-type models using Quantum Potentials. In this paper we describe the introduction of such quantum corrections within a full 3D drift diffusion simulation framework. We compare the two most popular quantum potential techniques: density gradient and the effective potential approaches, in terms of their justification, accuracy and computational efficiency. The usefulness of their 3D implementation is demonstrated with examples of statistical simulations of intrinsic fluctuation effects in decanano MOSFETs introduced by discrete random dopants. We also discuss the capability of the density gradient formalism to handle direct source-to-drain tunnelling in sub 10 nm double-gate MOSFETS, illustrated in comparison with Non-Equilibrium Green's Functions simulations.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Can the Density Gradient Approach Describe the Source-Drain Tunnelling in Decanano Double-Gate MOSFETs?

As MOSFETs are scaled into the deep sub-micron (decanano) regime, quantum mechanical confinement and tunnelling start to dramatically affect their characteristics. It has already been demonstrated that the density gradient approach can be successfully calibrated in respect of vertical quantum confinement at the Si/SiO₂ interface and can reproduce accurately the quantum mechanical threshold voltage shift. In this paper we investigate the extent to which the density gradient approach can reproduce direct source-drain tunnelling in short double gate MOSFET devices.     

Quantum correction for DG MOSFETs

The characteristics of modern semiconductor devices are strongly influenced by quantum mechanical effects. Due to this fact, purely classical device simulation is not sufficient to accurately reproduce the device behavior. For instance, the classical semiconductor equations have to be adapted to account for the quantum mechanical decrease of the carrier concentration near the gate oxide. Several available quantum correction models are derived for devices with one single inversion layer and are therefore only of limited use for thin double gate (DG) MOSFETs where the two inversion layers interact. We present a highly accurate quantum correction model which is even valid for extremely scaled DG MOSFET devices. Our quantum correction model is physically based on the bound states that form in the Si film. The eigenenergies and expansion coefficients of the wave functions are tabulated for arbitrary parabolic approximations of the potential in the quantum well. Highly efficient simulation of DG MOSFET devices scaled in the decananometer regime in TCAD applications is made possible by this model.     

A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench

In short-channel silicon-on-insulator metal-oxide-semiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOI MOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide.     

Simulations of Scaled Sub-100 nm Strained Si/SiGe p-Channel MOSFETs

This paper investigates scaled sub-100 nm strained Si channel p-type MOSFETs. For a 30–40% Ge content SiGe buffer, 1D Poisson-Schrödinger analysis indicates that the parasitic effects of the SiGe buffer are negligible in small devices with high n-type channel doping (>10¹⁷ cm^?3). The device published by IBM and calibrated by us has been scaled down to a 35 nm physical gate length and shows notable performance enhancement over the Si control MOSFET. Well-tempered MOSFET designs have also been adopted to study potential performance improvement associated with the introduction of a strained Si channel. These provide a performance improvement comparable with the scaled versions of the IBM devices for effective gate length down to 25 nm. Improved well engineering is required to suppress short channel effects during the scaling process.     

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm²/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.     

Improved device performance in a CNTFET using La$$_{}$$O$$_{3}$$3 high-$$\kappa $$κ dielectrics

The scaling of MOSFETs is an important and effective way for achieving high performance and low power consumption. One of the bottlenecks for scaling is the physical gate oxide thickness. This paper presents and evaluates a new method for scaling carbon nanotube field-effect transistors (CNTFETs) using \(\hbox {La}_{2}\hbox {O}_{3}\) as a new gate dielectric, which has excellent electrical properties. The proposed CNTFET is simulated using HSPICE. Some of the main digital and analog parameters such as current ratio, subthreshold swing (SS), transconductance, and intrinsic gain have been studied. The simulation results show that the proposed CNTFET outperforms present CNTFETs in terms of current ratio, transconductance, and intrinsic gain.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Analytical modeling and simulation of a linearly graded binary metal alloy gate nanoscale cylindrical MOSFET for reduced short channel effects

In the present era of miniaturization and low power devices, the approach of cylindrical gate MOS structure is in vogue among the researchers for enhancing the performance of nanoscale MOSFETs due to the inherent advantage of the cylindrical geometry compared to the conventional planar structures. In this work, for the first time, the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate has been incorporated in a cylindrical MOS and a new structure, the work function engineered gate cylindrical gate MOSFET (WFEG CG MOSFET) has been proposed. A detailed analytical modeling of this novel WFEG CG MOS structure has been presented based on the solution of two dimensional Poisson’s equation in cylindrical coordinates. An overall performance comparison of the WFEG CG MOS and normal CG MOSFET has been investigated to establish the superiority of the proposed WFEG structure over its normal CG counterpart in terms of increased immunity against short channel effects, reduced value of drain induced barrier lowering and enhanced current driving capability. The results of our analytical modeling are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Collapse of MOSFET drain current after soft breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.