薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

采用SiGe虚拟衬底高迁移率应变硅材料的制备和表征

研究了生长在弛豫Si0.79Ge0.21/梯度Si1-xGex/Si虚拟衬底上的应变硅材料的制备和表征,这一结构是由减压外延气相沉积系统制作的.根据双晶X射线衍射计算出固定组分SiGe层的Ge浓度和梯度组分SiGe层的梯度,并由二次离子质谱仪测量验证.由原子力显微术和喇曼光谱测试结果得到应变硅帽层的表面粗糙度均方根和应变度分别为2.36nm和0.83%;穿透位错密度约为4×104cm-2.此外,发现即使经受了高热开销过程,应变硅层的应变仍保持不变.分别在应变硅和无应变的体硅沟道上制作了nMOSFET器件,并对它们进行了测量.相对于同一流程的体硅MOSFET,室温下观测到应变硅器件中电子的低场迁移率显著增强,约为85%.     

一种新颖的应变Si沟道pMOSFET制作技术

在应变Si沟道异质结场效应晶体管（HFET）制作过程中，引入分子束外延（MBE）低温Si (LT-Si）技术，大大减少了弛豫SiGe层所需的厚度. TEM结果表明，应变Si层线位错密度低于1E6cm-2.原子力显微镜（AFM）测试表明，其表面均方粗糙度小于1.02nm.器件测试结果表明，与相同条件下的体Si pMOSFET相比，空穴迁移率提高了25%.     

Growth of strained-Si material using low-temperature Si combined with ion implantation technology

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with high-quality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.08Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 106 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.08Ge0.2 layer. By employing P+ implantation and rapid thermal annealing,the strain relaxation degree of the Si0.08Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Si/SiGe PMOSFET USING P^＋ IMPLANTATION TECHNOLOGY

Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor （PMOSFET） using P^＋ （phosphor ion） implantation technology is successfully fabricated. P^＋ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface, which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction （XRD） tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed, the sample appeared free of Threading Dislocation densities （TDs） within the SiGe layer to the limit of Transmission Electron Microscopy （TEM） analysis. Atomic Force Microscope （AFM） test of strained Si channel surface shows that Root Mean Square （RMS） is 1.1nm. The Direct Current （DC） characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.     

采用低温Si技术的Si/SiGe异质结P-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate

Crystal quality and strain distribution in SOI layer of conventional strained-Si on insulator (SSOI) and super-critical thickness strained-Si on insulator (sc-SSOI) were evaluated by in-plane X-ray diffraction (XRD), Raman spectroscopy, and other techniques. The surface defect distribution measured by wafer inspection system shows pit-type and line defects in both SSOI layers. More specifically, the sc-SSOI material has more line defects than conventional SSOI layers. Cross-hatched pattern defects were observed using X-ray topography (XRT) measurements. Raman mapping of 300 mm wafers shows the strain at the center of the wafer is larger than at the edge. In magnified close-up mapping, cross-hatched contrasts corresponding to misfit dislocations are observed, while the surface morphology is completely smoothed out. In-plane XRD measurements show the strain depth variations are quite uniform along the depth direction. The full width at half maximum (FWHM) of in-plane XRD peaks obtained from strained-Si layers is much larger than for un-strained SOI and bulk Si, reflecting poor crystal quality. SSOI was fabricated by the layer transfer of strained-Si on a virtual SiGe substrate. Therefore, we believe the crystal quality and strain distribution originate in the donor strained Si when virtual SiGe substrate is the starting material.