A simple method for on-chip, sub-femto Farad interconnectcapacitance measurement

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF     

On-chip capacitance measurement circuits in VSLI structures

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

Measurement of wall charge and capacitance variation for a single cell in the AC plasma display panel

Real-time dynamic measurements are performed on a single cell in a standard commercially available large plasma panel. The measurements determine cell response to variations in address pulses, sustain waveforms, or priming from neighboring cells. The wall-charge measurement indicates the internal dielectric surface charge and the capacitance measurement indicates the existence of a plasma in the gas volume. These measurements have shown that neighboring on cells can cause a large wall-charge transfer in off cells that results in reduced write and sustain voltage margins. Direct wall-charge measurements allows use of a simple technique for determination of the voltage transfer curve of the plasma cell which greatly aids device characterization. The capacitance measurement has shown that a plasma exists in commercial MgO panels for 10-15 µs after the discharge-current peak. The capacitance and wall-charge measurements can be combined to give simultaneous real-time results.     

基于前项补偿的电容层析成像数据采集系统

电容层析成像系统极板间的电容值相对于耦合电容相差近两个数量级,如何补偿耦合电容成为微小电容测量的难点之一。以12电极油水两相流电容层析成像系统为研究对象,在分析了电容层析成像系统原理的基础上,设计了电容层析成像数据采集系统,系统采用前项补偿方法完成了微小电容的测量,并根据实际测量过程所涉及的关键性问题进行了分析和讨论,通过实验验证了此方法是实用可行的,较好地解决了微小电容精确测量问题。     

基于前项补偿的电容层析成像数据采集系统

电容层析成像系统极板间的电容值相对于耦合电容相差近两个数量级，如何补偿耦合电容成为微小电容测量的难点之一。以12电极油水两相流电容层析成像系统为研究对象，在分析了电容层析成像系统原理的基础上，设计了电容层析成像数据采集系统，系统采用前项补偿方法完成了微小电容的测量，并根据实际测量过程所涉及的关键性问题进行了分析和讨论，通过实验验证了此方法是实用可行的，较好地解决了微小电容精确测量问题。     

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

New method for determining distribution of interface states in an MIS system

A general formula for the capacitance transient response in an MIS system was developed in order to apply the ICTS (isothermal capacitance transient spectroscopy) technique to an MIS diode. A new spectroscopic measurement method for determining the distribution of interface states is proposed and applied to an InAs MIS diode.     

基于电容检测技术的公路路面测厚仪的设计

分析了电容检测技术在公路路面厚度检测中的应用,利用环形电容传感器分别对自制的厚度不等的公路路面物理模型的厚度值进行检测,设计了以单片机为微处理器,兼有键盘、显示器、存储器等外围电路的电容测量电路对环形电容传感器的输出电容值进行采集,利用归一化处理方法依次得到不同厚度的路面模型的厚度值并显示出来。经过实验测试,该测量系统测量路面模型的厚度范围为0～15cm,测量精度达±3.0%,各项指标均达到了设计要求。     

On the error associated with the MIS method of capacitance measurement of surface state density

The inherent error associated with the deduction of surface capacitance from measured MIS capacitance is considered. It is shown that the systematic component of the experimental error does not restrict the range of applications of the technique whereas any random contribution can invalidate the measurement in certain cases.     

Refinements in the measurement of depleted generation lifetime

Constant capacitance measurement of bulk generation lifetime using MOS capacitors with a typical desktop computer controlled interface bus measurement system is shown to be practical for medium-and high-lifetime silicon. Refinements to the basic technique are developed to deal with surface generation, diffusion from the neutral bulk, and generation in the lateral surface depletion region.     

Determination of mobility in modulation-doped FET's using magnetoresistance effect

A simple measurement technique based on the magnetoresistance effect is developed to obtain the differential and average mobilities of modulation-doped field-effect transistors (MODFET's) with respect to gate bias voltage. The effect of parasitic series resistances can be neglected by using a low magnetic field. The measurement is not affected by parasitic gate capacitance and therefore constitutes an effective tool for characterizing fully processed ultra-short gate-length MODFET's.     

离子注入层少子寿命空间分布的测量

本文分析了非均匀掺杂衬底MOS电容对线性扫描电压的瞬态响应,提出了饱和电容法测量非均匀掺杂MOS电容少子产生寿命空间分布的方法.该方法的优点是测量与计算简单.     

Channel-length measurement technique based on a floating-gatedevice

By measuring the threshold voltage of the structure for several drawn channel lengths, ΔL is extracted. This technique is the translation of a capacitance measurement into a threshold measurement and as such is accurate and simple to perform. Since the technique does not involve a current flow through the transistor under test, it is especially advantageous for L_eff measurements on lightly-doped drain (LDD) and double-diffused drain (DDD) short-channel devices     

滚动轴承动态刚性的激光位移测定法

本文提出了一种以高精度、非接触激光位移传感器为核心的滚动轴承测量方法,可解决电容位移传感器测量中的非线性和对测量环境的敏感性问题。实验结果显示,该方法可准确获取滚动轴承动态刚性值,为滚动轴承的动刚性测试提供了一条新途径。     

Calibration Technique for Maximum Power Harvest of Passive Wireless Microsystems

A calibration technique for maximizing radio-frequency power harvest of passive wireless microsystems with a step-up transformer is proposed. We show that both the impedance and resonant frequency of the step-up transformer matching network can be adjusted by varying the capacitance of a shunt varactor placed at the secondary winding of the transformer to maximize power transfer from the antenna to the transformer and the output voltage of the transformer subsequently the power efficiency of the voltage multiplier. A low-power current-mode tuning technique and a maximum peak amplitude detection technique to allocate the optimal tuning capacitance at which the maximum power harvest exists are introduced. The transformer matching network has been designed in IBM CMRF8SF 130-nm 1.2-V CMOS technology, and its performance is validated using both simulation and on-wafer measurement results.     

Error in surface state determination caused by numerical differentiation of Q–V data

Numerical differentiation, which is used to obtain the low frequency capacitance by Ziegler and Klausmann's static technique, causes an error in evaluating the density of surface states. This error is largely suppressed by calculating the capacitance for the center of the measurement intervals ΔU_g.     

Inversion MOS capacitance extraction for high-leakage dielectricsusing a transmission line equivalent circuit

Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 Å requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxide's tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C_0x measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 Å     

Simulation for capacitance correction from Nyquist plot of complex impedance–voltage characteristics

The impression of series resistance on unipolar semiconductor device’s capacitance–voltage spectrum is discussed by conventional impedance and admittance analysis, and it is shown that series resistance may cause large errors in capacitance–voltage data. It is shown that the existence of such errors can be deduced from suitable complex impedance measurement obtained during the capacitance–voltage measurement process and this information can be used to correct the distorted capacitance values. A theoretical analysis and computer simulation are presented in order to illustrate the nature of the problem and the technique by which accurate depletion region capacitance can be obtained.