A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.     

Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors

Using InP-InGaAs heterojunction bipolar transistor (HBT) technology, we have successfully designed and fabricated a low-power 1:16 demultiplexer (DEMUX) integrated circuit (IC) and one-chip clock and data recovery (CDR) with a 1:4 DEMUX IC for 10-Gb/s optical communications systems. The InP-InGaAs HBTs were fabricated by a nonself-aligned process for high uniformity of device characteristics and producibility. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consist of approximately 1200 and 460 transistors, respectively. We have confirmed error-free operation at 10 Gb/s for all data outputs of both ICs. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consume only 1 W and 950 mW, respectively. These results demonstrate the feasibility of InP-InGaAs HBTs for low power high-integration optical communication ICs.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

12Gb/s 0.25μm CMOS低功耗1:4分接器

实现了一种能运用于光传输系统SONET OC-192的低功耗单级分接器,其工作速率高达12Gb/s.该电路采用了特征栅长为0.25μm的TSMC混和信号CMOS工艺.所有的电路都采用了源极耦合逻辑,在抑制共模噪声的同时达到尽可能高的工作速率.该分接器具有利用四分之一速率的正交时钟来实现单级分接的特征,减少了分接器器件,降低了功耗.通过在晶圆测试,该芯片在输入12Gb/s长度为231-1伪随机码流时,分接功能正确.芯片面积为0.9mm×0.9mm,在2.5V单电源供电的情况下的典型功耗是210mW.     

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX     

Highly conductive p + + ‐AlGaAs/n + + ‐GaInP tunnel junctions for ultra‐high concentrator solar cells

Tunnel junctions are key for developing multijunction solar cells (MJSC) for ultra‐high concentration applications. We have developed a highly conductive, high bandgap p ^{+ +} ‐AlGaAs/n ^{+ +} ‐GaInP tunnel junction with a peak tunneling current density for as‐grown and thermal annealed devices of 996 A/cm ² and 235 A/cm ², respectively. The J–V characteristics of the tunnel junction after thermal annealing, together with its behavior at MJSCs typical operation temperatures, indicate that this tunnel junction is a suitable candidate for ultra‐high concentrator MJSC designs. The benefits of the optical transparency are also assessed for a lattice‐matched GaInP/GaInAs/Ge triple junction solar cell, yielding a current density increase in the middle cell of 0.506 mA/cm ² with respect to previous designs. Copyright © 2014 John Wiley & Sons, Ltd.     

Martensitic Phase Transformation of Isolated HfO2, ZrO2, and HfxZr1 – xO2 (0 < x < 1) Nanocrystals

We previously reported that, during the reactions to make nanocrystals of HfO₂ and Hf‐rich Hf_xZr_{1 – x}O₂, a tetragonal‐to‐monoclinic phase transformation occurs that is accompanied by a shape change of the particles (faceted spherical to nanorods) when the temperature at which the reaction is conducted is changed from 340 to 400 °C. We now conclude that this concomitant phase and shape change is a result of the martensitic transformation of isolated nanocrystals in a hot liquid, where twinning plays a crucial role in accommodating the shape‐change‐induced strain. That such change was not observed during the reactions forming ZrO₂ and Zr‐rich Hf_xZr_{1 – x}O₂ nanocrystals is attributed to the higher driving force needed in those instances compared to that needed for producing HfO₂ and Hf‐rich Hf_xZr_{1 – x}O₂ nanocrystals. We also report here the post‐synthesis, heat‐induced phase transformation of Hf_xZr_{1 – x}O₂ (0 < x < 1) nanocrystals. As temperature increases, all the tetragonal nanocrystals transform to the monoclinic phase accompanied by an increase in particle size (as evidenced by X‐ray diffraction and transmission electron microscopy), which confirms that there is a critical size for the phase transformation to occur. When the monoclinic nanorods are heated above a certain temperature the grains grow considerably; under certain conditions a small amount of tetragonal phase appears.     

A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS

A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875 × 640 μm2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.     

Analysis of optical DEMUX characteristics based on four-wave mixingin semiconductor optical amplifiers

We have analyzed the basic characteristics of all-optical demultiplexing (DEMUX) based on four-wave mixing (FWM) in semiconductor optical amplifiers (SOAs) by solving a modified nonlinear Schrodinger equation by the finite-difference beam propagation method. Amplified spontaneous emission noise was not included in our model. The optimum pump pulsewidth for obtaining the high ON-OFF ratio is 1~3 ps for 1 ps, 250 Gb/s probe pulses. The shorter limit of the pulsewidth is due to detuning between the pump and probe frequencies, which is determined by the gain bandwidth of the SOA. In order to achieve faster DEMUX operation, an SOA with broader gain bandwidth is required. We also simulated pattern effects in the FWM signal. Power fluctuation in the FWM signal can be reduced by using a strong energy pump pulse and/or weak energy probe pulse. The energy fluctuation of the FWM signal decreases to less than 1% for a 30-bit, 250-Gb/s input probe pulse train with a pulse energy of 0.01 pJ. This small fluctuation should not disturb DEMUX operation. We have also examined DEMUX from time multiplexed signals by repetitive pump pulses. Strong energy pump pulses decrease the FWM signal intensity. However, there is no pattern effect due to gain saturation because the pump pulses are injected continuously     

A 40–50-GHz SiGe 1 : 8 Differential Power Divider Using Shielded Broadside-Coupled Striplines

This paper presents a 1 : 8 differential power divider implemented in a commercial SiGe BiCMOS process using fully shielded broadside-coupled striplines integrated vertically in the silicon interconnect stackup. The 1 : 8 power divider is only 1.12 $,times,$1.5 mm$^{2}$ including pads, and shows 0.4-dB rms gain imbalance and $≪ {hbox{3}}^{circ}$ rms phase imbalance from 40 to 50 GHz over all eight channels, a measured power gain of ${hbox{14.9}} pm {hbox{0.6}}$ dB versus a passive divider at 45 GHz, and a 3-dB bandwidth from 37 to 52 GHz. A detailed characterization of the shielded broadside-coupled striplines is presented and agrees well with simulations. These compact lines can be used for a variety of applications in SiGe/CMOS millimeter-wave circuits, including differential signal distribution, miniature power dividers, matching networks, filters, couplers, and baluns.      

Demultiplexing using an arrayed-waveguide grating for frequency-interleaved DWDM millimeter-wave radio-on-fiber systems

The frequency-interleaved dense- wavelength-division-multiplexing (DWDM) millimeter-wave (mm-wave) radio-on-fiber is an indispensable technique to improve the optical spectrum efficiency. We propose possible configurations of multiplexing and demultiplexing (DEMUX) schemes using an arrayed-waveguide grating (AWG) with two input and N output waveguides (N: total channel number). In this paper, we focus on the DEMUX scheme and experimentally demonstrate the DEMUX scheme using a commercially available AWG. In the experiment, 25-GHz-separated two-channel optical double sideband signals modulated by a 60-GHz millimeter-wave carrying a 156-Mb/s data are optically multiplexed by the frequency interleaving. The power penalty after DEMUX, which was due to interchannel interference, was less than 0.5 dB. We also made a transmission experiment over 25-km standard single-mode fiber (SMF). No noticeable power penalty in the received data due to chromatic dispersion of the transmission fiber was observed. This is because only the carrier and a sideband are detected in the proposed DEMUX scheme.     

用于光纤传输系统的10Gbit/s CMOS 1:8分接器

采用TSMC 0.25μm RF CMOS工艺设计了一个应用于光纤传输系统的10Gbit/s CMOS 1:8分接器.整个系统采用树型结构,由3级1:2分接器、2级1:2分频器、级间缓冲器和输入、输出接口电路构成.为了适应高速度的要求,所有电路全都采用源极耦合场效应管逻辑来实现.使用SmartSpice进行了仿真,结果表明:在电源电压为3.3V时,电路的最高工作速率可以达到10Gbit/s,电路功耗约为800mW.     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

Wavelength-division multi/demultiplexer utilizing optically activecrystals

A wavelength-division multi/demultiplexer (W-MUX/DEMUX) utilizing optically active crystals is proposed and studied. It is shown that using two or more optically active crystals having different rotary powers and dispersions is effective for providing design freedom and for easy assembly of the W-MUX/DEMUX. A design for a two-wavelength W-MUX/DEMUX is also discussed. Based on this design, a W-MUX/DEMUX that multiplexes or demultiplexes light with wavelengths of 0.8 and 1.1 μm was fabricated. The insertion losses are 1.6 and 3.1 dB at wavelengths of 0.8 and 1.1 μm, respectively. Crosstalk attenuation of 13 dB or more is obtained at these wavelengths     

Multimode optical demultiplexer for DWDM with liquid crystal enabled functionalities

We have developed a liquid-crystal-based multimode optical demultiplexer (DEMUX) with additional functionalities such as switching and power equalization. Demultiplexing 16-channel 100-GHz-spaced signals into a 62.5-/spl mu/m multimode-fiber array is demonstrated. The central wavelength of each channel is designed according to the International Telecommunication Union grid. Adjacent channel crosstalk is less than -30 dB. The average 1and 3-dB passbands of the DEMUX are 12.5 and 22.5 GHz, respectively. A maximum extinction ratio of 16.2 dB is achieved. Different channels can be switched with rise and fall times of /spl sim/10 and /spl sim/70 ms, respectively. The outputs of the channels are equalized to -65 dBm. The variation between different channels reduced from /spl sim/10 dB to less than 0.5 dB.     

Electronic structure of Ge1 − x − ySixSny ternary alloys for multijunction solar cells

Ternary group‐IV alloys have a wide potential for applications in infrared devices and optoelectronics. In connection with photovoltaic applications, they are among the most promising materials for inclusion in the next generation of high‐efficiency multijunction solar cells, because they can be lattice matched to substrates as GaAs and Ge, offering the possibility of a range of band gaps complementary to III–V semiconductors. Apart from the full decoupling of lattice and band structures in Ge_{1 − x − y}Si_xSn_y alloys, experimentally confirmed, they allow preparation in a controllable and large range of compositions, thus enabling to tune their band gap. Recently, optical experiments on ternary alloy‐based films, photodetectors measured the direct absorption edges and probed the compositional dependence of the direct gap. The nature of the fundamental gap of Ge_{1 − x − y}Si_xSn_y alloys is still unknown, as neither experimental data on the indirect edges nor electronic structure calculations are available, as yet. Here, we report a first calculation of the electronic structure of Ge_{1 − x − y}Si_xSn_y ternary alloys, employing a combined tight‐binding and virtual crystal approximation method, which proved to be useful to describe group‐IV semiconductor binary alloys. Our results confirm predictions and experimental indications that a 1eV band gap is indeed attainable with these ternary alloys, as required for the fourth layer plan to be added to present‐day record‐efficiency triple‐junction solar cells, to further increase their efficiency, for example, for satellite applications. When lattice matched to Ge, we find that Ge_{1 − x − y}Si_xSn_y ternary alloys have an indirect gap with a compositional dependence reflecting the presence of two competing minima in the conduction band. Copyright © 2013 John Wiley & Sons, Ltd.     

12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits

A 12.5 Gbps 1:16 demultiplexer(DEMUX) integrated circuit is presented for multi-channel high-speed data transmission.A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques,the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz.The circuit is realized using 1μm GaAs heteroj unction bipolar transistor technology with die area of 2.3×2.3 mm~2.