Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-μm SiGe BiCMOS process and is characterized at 900 MHz     

A single-chip 900-MHz spread-spectrum wireless transceiver in1-μm CMOS. II. Receiver design

For pt. I see ibid., vol. 33, no. 4, April 1998. A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is -8.3 dBm. In active mode, the receiver takes 120 mA from 3 V     

A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

Design of a low-power ZigBee receiver front-end for wireless sensors

This paper describes the design of a low cost, low-power ZigBee receiver for wireless sensor networks. The receiver consists of a low-noise amplifier, a pair of down-conversion mixers, and a pair of variable-gain low-pass filters. The LNA has a single-ended input, eliminating the need for an off-chip balun, a differential output, allowing it to drive a double-balanced mixer, and it uses noise cancellation to improve its noise performance. The mixers are double-balanced passive mixers to improve the receiver linearity and decrease its power consumption and flicker noise. Finally, the filter is a third-order Butterworth G_m-C filter with a variable input transconductor to provide gain programmability for the receiver. The design is made using 130 nm CMOS technology with 1.2 V supply. Simulation results show that the receiver can achieve a sensitivity level of −97 dBm while consuming only 6 mA.     

WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-μm 45-GHz f_T SiGe BiCMOS process     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

Elitist nondominated sorting genetic algorithm based RF IC optimizer

An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process.     

A new high-dynamic range dual-loop power-to-current amplifier

The design and performance of a balanced amplifier with a dual differential feedback loop in a high-frequency BiFET (bipolar-field effect transistor) process (f_T=3 GHz) is presented. By means of this dual feedback loop, a linear, accurately known input impedance is obtained, combined with a high-output impedance. The noise figure of the realized amplifier is lower than 3 dB. The amplifier is especially intended for low-noise, low-distortion termination of antennas, cables, or filters and for driving bipolar switching mixers up to frequencies well above 100 MHz     

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

A 30 GHz MMIC receiver for satellite transponders

The development of 30-GHz-band monolithic microwave integrated circuits (MMICs) and multichip MMIC modules (low-noise amplifier and frequency converters) is reported. A 30-GHz-band full-MMIC receiver for satellite transponders was successfully constructed using the MMIC modules and the performance of the full-MMIC receiver is evaluated. Test results verify its successful performance as a satellite receiver system. The design and performance of the MMICs (a two-stage amplifier, an image rejection mixer, and a frequency multiplier), of multichip-type MMIC modules (a 30-GHz-band low-noise amplifier module with 30 dB gain and 8.2 dB noise figure, and an image rejection frequency converter with a 10 dB conversion loss and an 18 dB image rejection ratio) and of the full-MMIC receiver, which weighs 1/6 as much as a conventional hybrid integrated circuit are presented     

A direct-conversion receiver for DVB-H

A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.     

3 V, 28 mW Si-bipolar front-end IC for 900 MHz homodyne wirelessreceivers

A 900 MHz homodyne receiver front-end bipolar chip is presented. The circuit consists of a low-noise amplifier and two double-balanced mixers for in-phase and quadrature channels. The power supply voltage is 3 V and power dissipation is 28 mW. The measured performance includes 33.5 dB voltage gain, a 3.1 dB noise figure, -13 dBm input referred IP3, -95 dB LO leakage into the RF port on wafer probing, and less than 0.1 dB I/Q magnitude imbalance     

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.     

Integrated receivers for wireless communications: A review

A review is presented that addresses the circuit-design aspects of integrated receiver front ends with their CMOS realization in mind. Performance data on specific front ends and their individual units are given with emphasis on low-noise amplifiers, mixers, and voltage-controlled local oscillators. Promising lines of research and development are identified.     

Integrated X-band Sweeping Superheterodyne Receiver

The development of an integrated low-noise sweeping superheterodyne receiver is described. Based upon a receiver performance tradeoff study, a group of components were designed and integrated within a single housing occupying 5.9 in/sup 3/, less connectors. The integrated receiver weighs 6.4 oz, including magnets, and contains the following components: a wide-band low-noise tunnel-diode amplifer (TDA), an image-rejection balanced mixer, a varactor-tuned Gunn oscillator, a four-stage IF amplifier, and a quasi-complementary IF output filter. The housing also contains an interstage ferrite isolator, a bias distribution network with subminiature potentiometers, and a branch-line coupler. This coupler permits the injection of an external oscillator and allows the system to be evaluated outside the band covered by the internal Gunn oscillator. This receiver is the first kind to integrate within a minimum volume all the components necessary for a wide-band low-noise rapid-scan X-band imageless superheterodyne receiver. Varactor tuning permitted the entire receiver to be integrated in a package having about one fifth the weight and two fifths the volume of other similar receiver designs (e.g., a receiver utilizing a YIG-tuned oscillator).     

IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver

A major contributor to degraded input-referred second-order intercept point (IIP2) in integrated RF systems-on-chips is local oscillator (LO) leakage to the input of RF circuits. In this brief, we present a digital calibration technique for improving IIP2 by injecting controlled dc offset at the mixer output through a three-port network of switched-capacitor filters. The dc offset at mixer output gets up-converted to LO frequency at the input of RF circuits due to poor reverse isolation of the receiver front-end. By controlling the amplitude of the injected dc, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis is presented and supported by measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process. Calibrated IIP2 of 50 dBm is reported for the receiver at low-noise amplifier input.     

Receiver Front-End Circuits for Future Generations of Wireless Communications

In this paper, new receiver concepts and CMOS circuits for future wireless communications applications are introduced. The concepts derived are applied to a few classes of wireless communications standards that are broad-band at radio frequencies and/or require a broad-band baseband circuitry. Multimode multiband operation and adaptivity as key requirements for future generation receivers are highlighted throughout the paper. The tradeoffs between power consumption, noise figure and linearity performance of low-noise amplifiers, mixers, and intermediate frequency filters are considered too.     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.     

2.4-GHz receiver for sensor applications

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.