On the forward current-voltage characteristics of p+-n-n+ (n+-p-p+) epitaxial diodes

The forward-biased current-voltage characteristics of p⁺-n-n⁺ and n⁺-p-p⁺ epitaxial diodes are derived theoretically. Effects of the energy-gap shrinkage, the high-low junction built-in voltage, the high-level injection, and the minority-carrier life time on the forward-biased current-voltage characteristics are included. Good agreements between the theoretically derived results and the experimental data of Dutton et al. are obtained. The developed theory predicts that the leakage of the high-low junction is dominated by the recombination of minority carriers in the highly doped substrate, not by the recombination of minority carriers in the high-low space charge region, which is opposite to the previous prediction of Dutton et al.     

Forward transient characteristics of gold-doped silicon p+-n-n+diodes

The transient response of high-resistivity long-base low-lifetime p⁺-n-n⁺silicon diodes was examined experimentally. The diodes were doped with gold in order to reduce the minority carrier lifetime. Voltage oscillations were observed at different current levels. A large inductive effect was shown to exist when the diode was forward biased in a negative resistance region of the dc voltage-current characteristics.     

High-frequency oscillations of p++-n+-n-n++avalanche diodes below the transit-time cutoff

According to Read, n⁺⁺-P⁺-i-P⁺⁺diodes should oscillate at special high frequencies determined by carrier transit time in the space-charge layer. Oscillations not affected by transit time were observed with p⁺⁺-n⁺- n-n⁺⁺silicon diodes. The corresponding current-voltage characteristic revealed a negative resistance setting in at a critical current. Theoretical considerations show that one-sided avalanche injection in n⁺⁺-p⁺-p⁺⁺structures may lead to a slight negative resistance for carrier concentrations smaller than the impurity concentration and for certain widths of the depletion layer. This type of negative resistance disappears in n⁺⁺-p⁺-i-P⁺⁺structures, but with increasing injection multiplication is induced in the intrinsic layer. Therefore the carrier space-charge is reduced and a negative resistance appears at a critical current density. The onset of this second injection is an upper current limit of the Read transit-time mode. The frequency range of oscillations due to avalanche space-charge feedback generally will not be separated from the range of transit-time oscillations. Thus, it must be judged carefully which mechanism is responsible for observed high-frequency oscillations. On the other hand, space-charge feedback may give additional stability to the transit-time mode.     

Current transport characteristics of SiGeC/Si heterojunction diode

The characteristics of heterojunction diodes fabricated from p-type epitaxial Si_0.07Ge_0.91C_0.02 alloy grown by molecular beam epitaxy on n-type Si(100) have been examined by using current-voltage, capacitance-voltage, and Hall effect measurements. The SiGeC/Si heterojunction diode shows good rectification with nearly ideal forward bias behavior and low reverse leakage currents compared to Ge/Si heterojunction diodes. The temperature dependence of the current-voltage behavior indicates that the principle conduction mechanism is by electron injection over a barrier. Reverse breakdown occurs by the avalanche mechanism     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

Modeling of minority-carrier surface recombination velocity atlow-high junction of an n+-p-p+ silicon diode

Modeling of recombination velocity of minority carriers at the p-p ⁺ low-high junction end of the p-base region of n⁺-p-p⁺ silicon diodes is carried out by taking the minority-carrier recombination effects in the space-charge region (SCR) of the low-high (L-H) junction into account. Solving Poisson's equation in the SCR numerically revealed that the SCR is composed of an accumulation layer on the p side and a depletion layer on the p⁺ side. Generally, the depletion layer is very thin as compared with the accumulation layer, and the built-in potential across the depletion layer never exceeds the thermal voltage, i.e. kT/q. Further, the minority-carrier recombination in this layer is also insignificant. For most L-H junction-based silicon devices, in practice, the minority-carrier recombination in the accumulation layer controls the value of the effective minority-carrier recombination velocity (S_eff) at the back surface of the p-base region and the influence of the recombination in the heavily doped p⁺ region is less significant     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Voltage distribution in n+-n-n+and metal-cathode n-n+GaAs X-band oscillators using a SEM

Time-averaged and dynamic results have been obtained in n⁺-n-n⁺and metal cathode n-n⁺GaAsX-band devices, using a new voltage measurement scheme in the SEM. The n⁺-n-n⁺devices show accumulation layer propagation, and the metal-cathode devices show a trapped dipole domain behavior.     

20-GHz high-power GaAs DDR-IMPATT diodes with a p+-p-n-n+structure

GaAs DDR (double-drift-region)-IMPATT diodes have been made by using epitaxial wafers with a p⁺-p-n-n⁺structure, which was made by successive liquid-phase epitaxy of p⁺, p, and n layers on n⁺substrate in one heat cycle. On the diodes with copper heat sink, the maximum CW output power of 1.2 W was obtained at 21 GHz with the efficiency of 15.6 percent.     

Surface state and surface recombination velocity characteristics of Si-SiO2interfaces

A new device has been used to study the surface recombination velocity and surface state characteristics of Si-SiO2interfaces. The device consists of an epitaxially-formed junction diode. When the junction is forward-biased, minority carriers are injected from the heavily-doped substrate into the lightly-doped epitaxial region. The thickness of the epitaxial region is much less than the diffusion length for minority carriers. Thus, the diode current for a given junction forward bias is directly proportional to surface recombination velocity at the Si-SioO2interface. A gate electrode over the SiO2has been included to vary surface potential. Thus, this new device permits one to simultaneously study MOS capacitance-voltage characteristics as well as surface recombination velocity. The capacitance-voltage characterics indicate the surface states exhibit a quasi-continuous energy distribution. N-type surfaces exhibited donor levels lying in the range of ∼0.15 to ∼0.45 eV above the valence band; their density was found to vary from ∼5 × 10¹²to 5 × 10¹³states/cm²/eV. In contrast, p-type surfaces exhibited acceptor levels lying in the range of ∼0.15 to ∼0.45 eV below the conduction band; their density was comparable to those observed on n-type surfaces. The maximum value of surface recombination velocity was found to vary from 3 × 10³to > 10⁴cm/s. Surface recombination velocity was found to correlate directly with surface state density.     

Characteristics of siliconn+-n--n+ diode with sub-micrometer n- region

In this paper, the I-V characteristics of silicon n⁺-n ^--n⁺ diode are investigated as a parameter of the length of the n^- region. This diode with shorter n^- region than 1 μm has the ohmic characteristics until reaching high electric field in spite of the existence of numerous space-charges in the n^- region, for the first time in this report. This conductance of the diode is inversely proportional to the third power of the length of the n^- region. The experimental results are in good agreement with an analytical calculation including the diffusion term of carriers injected from the n+ regions to the n^- region. However, the diode with longer n^- region than 2 μm shows the space-charge-limited conduction which is the same as earlier reports     

A first order theory of the p+-n-n+edge-illuminated silicon solar cell at very high injection levels

A first order theory of the edge-illuminated p⁺-n-n⁺silicon solar cell under very high injection levels has been derived. The very high injection level illuminatedJ-Vcharacteristic is derived for any general base width to diffusion length (W/L) ratio and it includes the minority carrier reflection by the n-n⁺high-low junction. The beneficial effects of the high-low junction are shown to be significant until extremely high injection levels are reached. The theoretical dependencies of Jscand Vocon temperature, incident intensity, and base resistivity are derived and discussed in detail. Some experimental results are given and these are discussed in relation to the theory.     

Characteristics of an all-implanted p+-n-n+solar cell

This work presents the main electrooptical parameters of a p⁺-n-n⁺single-crystalline silicon solar cell, whose front p⁺-n junction and the backside n-n⁺contact were fabricated through masked ion implantation of boron (¹¹B+) and phosphorus (³¹p+), respectively. The distinctive feature of the cells consists of the use of the front junction silicon dioxide mask as an AR layer in the finished devices.     

In-situ low energy BF2+ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF2+ in silicon molecular beam epitaxy (MBE) is described. BF2+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF2+-doped epitaxial material showed hard reverse breakdown characteristics.     

Near state-of-the-art power in p+-n-n+D-band IMPATT diode on a wafer with ramped n-n+interface

Fabrication of near state-of-the-art (P0= 110 mW, η = 4.85 percent p⁺-n-n⁺D band (f = 124 GHz) Si IMPATT diode on a wafer with ramped n-n⁺interface is described. Introduction of a critical annealing step, prior to p⁺diffusion, in the fabrication sequence of the diode has been found to yield the above results. Possible reasons for power and efficiency enhancement has been discussed.     

Diffusion and recombination 1/f noise in long n+-p Hg1—xCdxTe diodes

1/f noise in long n⁺-p Hg1-xCdxTe diodes with x = 0.30 is studied at 193 K. The 1/f noise is considered to be generated by diffusion and recombination fluctuations. A distinction is made between cases a (all minority carriers contribute to the 1/f noise) and b (only the excess minority carriers contribute to the 1/f noise). Measurements on long nonplanar diodes show that case a is valid, indicating that all minority carriers contribute equally to the 1/f noise; this should be valid for any long-junction device in which the current flow is by diffusion and recombination of minority carriers. The lifetime τnof the electrons in the p-region is measured by the input impedance method, and the Hooge parameter αHof the device is evaluated. τnis of the order of 10^-6to 10^-7s and depends somewhat on bias. Near zero bias αHis of the order of 5 × 10^-3in close agreement with Handel's coherent state 1/f noise theory, which yields αH= 4.6 × 10^-3. Due to the nonplanar geometry of the studied diodes, the measurement of τnis not always equally reliable. Larger values of τnare accompanied by larger values of αH, because the noise measurements give αH/τn, and its value practically independent of bias. We also evaluated τnby putting αH= 4.6 × 10^-3; the τnvalues are then much closer and agree rather well with Honeywell lifetime tables. Preliminary measurements at 113 K also indicate coherent state 1/f noise, whereas data at 273 K give αH= 5 × 10⁵, in agreement with the Umklapp 1/f noise theory.     

Characterization of shallow silicided junctions for sub-quartermicron ULSI technology. Extraction of silicidation induced Schottkycontact area

The current-voltage (I-V) characteristics of shallow silicided p ⁺-n and n⁺-p junctions are presented. In the former the diode behavior was same as in nonsilicided junction, while drastic change in diode I-V was observed in the latter. The formation of Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n⁺-p junction in the forward bias region. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, masking thereby the effect of Schottky contact. The leakage current in n⁺-p diodes was higher than in nonsilicided diodes by two orders of magnitude and this is consistent with the formation of Schottky contact via titanium or titanium-silicide penetrating into the p-substrate and generating trap sites. There is no increase in the leakage current and no formation of Schottky contact in case of the p⁺-n junction. The Schottky contact amounting to less than 0.01% of the total junction area and not amenable for SEM or TEM observation was extracted for the first time by simultaneous characterization of forward and reverse characteristics of silicided n ⁺-p diode     

Improved performance of implanted n+-p Hg1-xCdxTe photodiodes using insulated field plates

Using insulated field plates, we have demonstrated that surface leakage had been limiting the RoA of our ion-implanted n+ -on-p (Hg, Cd) Te photodiodes. This leakage is believed to be tunneling current across a pinched-off depletion region at the surface. We have used gated diodes to eliminate leakage and improve RoA to the diffusion limit at 77°K for Hg0.8Cd0.2Te photodiodes.     

Formation of planar n+pockets in GaAs for mixer diode fabrication

A novel technique has been developed to produce n⁺"pockets" in semi-insulating GaAs bulk material. This technique has produced thick pockets of highly conducting epitaxial material on the substrate surface. The pockets were formed by the growth of a liquid-phase epitaxial (LPE) layer into holes which had been etched into the substrate. Surface uniformity was obtained by chemo-mechanically polishing the substrate surface under tightly controlled conditions. Polishing rates as low as 0.2 µm/min have been obtained. Photographs taken of the pocket cross-sectional area have revealed that growth occurred throughout the entire pocket region. Growth was even found to have occurred along the irregularly shape walls of the pockets. The continuous growth throughout the pockets coupled with the subsequent polishing of the substrate have produced exceptionally smooth and planar surfaces. Thicknesses as great as 10 µm have been obtained for the n⁺pockets using this technique. Mixer diodes have been fabricated onto these layers and tested. Preliminary dc measurements taken on these devices have yielded a zero-biased cutoff frequency (Fco) of 800 GHz with a series resistance (Rs) of 6 Ω and a zero-biased capacitance (C0) of 30 fF.