多晶硅加热法评价金属互连线电迁移寿命

采用一种新颖的方法——多晶硅加热法评价了金属连线的电迁移（EM）寿命．用该方法得到的结果与传统封装测试法得到的结果进行了对比，两者有相当好的一致性．同时，测试时间不到封装测试的1‰．说明多晶硅加热法是一种非常有效的EM评价方法．由于该方法是晶片级测试，而且测试时间非常短，所以采用这种方法可以实现对金属互连线质量的在线实时监控．     

多晶硅加热法评价金属互连线电迁移寿命

采用一种新颖的方法--多晶硅加热法评价了金属连线的电迁移(EM)寿命.用该方法得到的结果与传统封装测试法得到的结果进行了对比,两者有相当好的一致性.同时,测试时间不到封装测试的1‰.说明多晶硅加热法是一种非常有效的EM评价方法.由于该方法是晶片级测试,而且测试时间非常短,所以采用这种方法可以实现对金属互连线质量的在线实时监控.     

集成电路互连线电迁移测试方法与评价

介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。对加速寿命试验进行了分析和评价。分析表明,加速寿命试验方法存在高应力条件与正常工作条件下互连线电迁移中金属离子扩散机制不同、BLACK方程的使用范围有限、受试件特殊结构影响和电阻温度系数TCR随温度变化等问题。介绍了一种改进方法。详细介绍了移动速度试验,指出了其在互连线电迁移研究中的应用。     

集成电路中的抗电迁移研究

本文简要介绍了集成电路中电迁移的原理、失效模式、物理模型、各种因素对电迁移寿命的影响及电迁移的预防措施。     

改进的电迁移独立失效元模型

当前被广泛采用的描述电迁移失效的独立失效元模型存在很多缺陷．本文根据电迁移失效的物理机制和一些必要的假设，对其进行了一些改进．主要是以三叉点代替晶粒作为独立失效元，并不再假设单个失效元的中值失效时间与晶粒大小无关．对连线宽度、晶粒大小与电迁移寿命的模拟结果都比传统的独立失效元模型更符合实验事实．     

电迁移致无铅钎料微互连焊点的 脆性蠕变断裂行为

研究了电迁移条件下不同电流密度(0.8~1.27×10⁴A/cm²)和通电时间(0~96 h)对无铅钎料模拟微互连焊点的蠕变断裂行为的影响.研究结果发现,电迁移作用加速了焊点的蠕变断裂过程,随着电迁移通电时间的延长及电流密度的增加,其蠕变应变速率显著增大,而蠕变寿命逐渐缩短;电迁移还导致焊点蠕变断裂机制发生明显变化,在高电流密度或长时间通电的电迁移后,微互连焊点在服役条件下会发生由延性断裂向脆性断裂的转变.     

具有冗余设计的铜互连线电迁移可靠性评估

铜互连的电迁移可靠性与晶粒结构、几何结构、制造工艺以及介质材料等因素有着密切的关系。分别试制了末端有一定延伸的互连线冗余结构设计的样品,以及无冗余结构的互连线样品,并对样品进行了失效加速测试。测试结果显示,采用冗余结构设计的互连线失效时间更长,具有更好的抗电迁移可靠性。对冗余结构的失效模式进行了讨论,并结合互连线的制造工艺,指出采用冗余结构设计的互连线可以在有效改善互连线的电迁移特性,而且不会引入其他影响可靠性的因素,是一种有效提高铜互连电迁移可靠性的方法。     

铜互连电迁移失效的研究与进展

Cu/低k互连的电迁移失效与互连材料、工艺、结构和测试条件都有着密切的联系。论述了近年来铜互连电迁移可靠性的研究进展,讨论了电迁移的基本原理、失效现象及其相关机制和微效应以及主导失效的机制——界面扩散等,同时探讨了改善铜互连电迁移性能的各种方法,主要有铜合金、增加金属覆盖层及等离子体表面处理等方法,并指出了Cu互连电迁移可靠性研究有待解决的问题。     

电迁移引起的倒装芯片互连失效

采用倒装芯片组装菊花链器件研究了高电流密度条件下Al互连的失效问题,分析了不同电迁移条件下,由于金属原子的迁移造成的Al互连微结构的变化。在9.7×105A/cm2电流密度强度条件下,钝化窗口位置的Al原子发生电迁移,在电子风力的作用下,Al原子沿电子流方向扩散进入Al互连层下方的焊料中。同时,随着电流加载时间的延长,化学位梯度和内部应力的作用致使焊料成分向Al互连金属扩散,Al互连金属层形成空洞的同时其成分发生变化。     

多层金属化系统中蓄水池效应对电迁移寿命的影响

在W通孔的多层金属化系统中,金属离子的蓄水池效应对其电迁移寿命的影响很大,文中设计制作了12种不同的蓄水池结构,并进行了电迁移实验.着重考察蓄水池面积、通孔位置、通孔数目对互连线电迁移寿命的影响,得出蓄水池的面积是影响电迁移寿命的主要因素.     

The evolution of the resistance of aluminum interconnects during electromigration

Resistance monitoring is a traditional method to investigate electromigration failure. It is important to understand how much information can be extracted from the data generated by these experiments. To this end, precision resistance measurements were included as part of accelerated electromigration tests performed inside of a high voltage scanning electron microscope (HVSEM). Twenty-two passivated Al interconnects were tested at 30 mA/μm² and at two temperatures, half at 212°C and half at 269°C. During every test, our automated apparatus stored images of each 300 μm long structure several times per hour. The resistance of each line was also precisely measured and recorded. Changing the temperature affected only the time scale of the resistance evolution. There were resistance changes before voids formed that were neither due to temperature fluctuations nor solute effects. In most cases, the nucleation of the first void to form in a line was signaled by an increase in the time derivative of the resistance. Due to the strong effect of void shape, the void volume could not be determined by the magnitude of the resistance change. The width of a void (transverse to the line) rather than the volume largely determined the resistance change.     

Shape effect on electromigration in VLSI interconnects

The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.     

Skin effect of on-chip copper interconnects on electromigration

A simple model is derived to evaluate skin effect of on-chip copper interconnects on electromigration. The result gives the range of frequency in which skin effect on electromigration need to be taken into consideration.     

Effects of length scaling on electromigration in dual-damascene copper interconnects

The electromigration short-length effect in dual-damascene Cu interconnects has been investigated through experiments on lines of various lengths (L), being stressed at a variety of current densities (j), and using a technologically realistic three-level structure. This investigation represents a complete study of the short-length effect after a well-developed dual-damascene Cu process. Lifetime measurement and resistance degradation as a function of time were used to describe this phenomenon. It has been found that the sigma of log–normal distribution increased as the current density–length product decreased. The statistical distribution of the critical volume fits the sigma curve well. Lower jL² values show large sigma values because of back-stress-induced TTF (time-to-fail) dispersion. A simplified equation is proposed to analyze the experimental data from various combinations of current density and line length at a certain temperature. The resulting threshold–length product (jL)_C value appears to be temperature dependent, decreasing with an increase in temperature in a range of 250–300 °C.     

Mechanism of electromigration failure in submicron Cu interconnects

This paper reports on two different electromigration-failure mechanisms competing in Cu interconnects. Accelerated electromigration tests are conducted on identical single-level, 0.25-μm Cu interconnects with SiN or SiCN passivation. The results indicate that the failure mechanism can vary with the interface condition of the capping layer. The first failure mechanism, seen primarily in SiN-capped samples, is characterized by extensive interface damage, believed to be a result of failure led by interface electromigration. In this failure mode, damage initiates at the capping interface but gradually spreads along all interfaces of the Cu to form an isolated strand. The competing failure mechanism, found in SiCN-capped samples, is characterized by the formation and growth of a localized void without extensive interface damage. The absence of interface damage, in addition to the higher activation energy for failure, suggests that the failure occurs at a more localized inhomogeneity than the interface, such as grain boundaries. While the exact mechanism of how the capping layer suppresses one mechanism and promotes the other is unknown, this study reveals that the passivation-interface material and condition have a decisive role in determining the failure mechanism in Cu interconnects.     

Effect of low k dielectrics on electromigration reliability for Cu interconnects

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport dominated by diffusion at the Cu/SiN_x cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)_c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM and found to correlate well with EM lifetime and the (jL)_c product of low-k interconnects.     

Microstructural and surface effects on electromigration failure mechanism in Cu interconnects

It is shown that changes in the microstructure of Cu interconnects lead to qualitative variation in electromigration damage kinetics - from the formation of the open circuit to continuous damage not leading to failure. Surface diffusion acting simultaneously with grain boundary mass transport is shown to be critical for damage formation. Activation energy of electromigration was measured to be 0.95 eV.     

Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects

Electrostatic discharge events can degrade the electromigration (EM) reliability of devices. Transmission line pulsing stress analysis is used to evaluate electrostatic discharge robustness of copper (Cu) interconnects and the impact to EM performance. Compelling evidence from transmission electron microscope data suggests the change in the microstructure of the interconnects explains the creation of latent EM failures.     

A compact model for early electromigration failures of copper dual-damascene interconnects

A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.     

高温恒定电流电迁移可靠性试验及结果分析

介绍了评价电迁移可靠性的高温恒定电流试验方法,以电阻值超过初始值10％为失效判据,对某工艺的几组样品进行可靠性评价。该试验方法简便、可靠,适用于亚微米和深亚微米超大规模集成电路的可靠性评价。