基于无采样保持和运放共享的10-bit 50-MS/s亚采样流水线模数转换器

摘要：本文采用提出的面积和功耗优化结构,设计了一个10-bit 50-MS/s的流水线模数转换器。本设计将采样保持和第一级转换电路融合为一个模块,既省去了前端采样保持电路,又避免了第一级中余差放大电路和子模数转换器延时路径需要匹配的问题,该模块具有功耗低稳定性高的特点。为了进一步降低面积和功耗,相邻两级间采用运放共享结构,该结构具有运放失调电压和级间串扰影响小的特点。该10-bit模数转换器的实现仅采用了四个运放。测试结果表明,当采样率为50MHz、输入为奈奎斯特频率时,获得52.67dB SFDR和59.44dB SNDR。当输入频率上升到两倍奈奎斯特频率时,该模数转换器仍然保持了稳定的动态性能。本设计采用0.35μm CMOS工艺实现,芯片有效面积仅为1.81mm2,50MHz采样率3.3V供电时功耗为133mW。     

一种采用开关内置双输入MDAC的10b 80 MS/s 运放共享流水线模数转换器

在0.18-μm CMOS工艺下设计了一种10位80MHz采样频率的运放共享流水线模数转换器,提出了一种开关内置的双输入运放共享的MDAC,从而有效的消除了传统结构存在的无法复位和级间干扰通路的问题。测试结果显示,本设计的模数转换器的SNDR可以达到60.1dB,无杂散动态范围可以达到76dB,有效位为9.69 bit,在整个奈奎斯特带宽内有效位均高于9.6bit。芯片核心面积为1.1 mm2,在1.8 V电源电压下功耗为28mW。     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.     

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-/spl mu/m CMOS process occupies an active area of 4.2mm/sup 2/, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively.     

A 10$sim$ 15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration

Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain and offset as in the multi-path time-interleaved ADC. For high-speed operation at all gain settings, a constant-bandwidth switched-capacitor VGA is implemented with variable-bandwidth opamps, and its gain and offset are digitally calibrated in background using signal-dependent pseudo-random noise (PN) dithering and chopping techniques. A three-stage VGA adjusts its gain instantly from $times$ 1 to $times$ 32 depending on the sampled input level, and improves the INL of a 10-bit ADC from 24 to 0.9 least significant bits (LSBs) at a 15-bit level for the low-level input. The resulting 10 $sim$ 15-bit 60-MS/s ADC needs no input sample-and-hold (S/H) stage, and achieves a system noise of $-$80 dBFS with a gain set to $times$ 32. A prototype chip in 0.18-$muhbox{m}$ CMOS occupies an active area of $3.0times 2.0 hbox{mm}^{2}$ , and consumes 300 mW at 1.8 V including digital calibration logic.