Low-voltage arithmetic units based on fully depleted SOI CMOS nanotransistors

Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits

The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 μm technology device a good matching with the fsm was found.     

Short-channel effect in fully depleted SOI MOSFETs

The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness     

Mobility-field behavior of fully depleted SOI MOSFET's

This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q_i=C_ox(V_GS-V_TH), for the inversion charge density in FD SOI is examined and experimentally confirmed     

Low-power high-performance double-gate fully depleted SOI circuitdesign

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added back-channel leakage; and how the coupling between the front- and back-gates affects circuit reliability. Our analyses over different technology generations using the MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability in controlling leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for best leakage control. Moreover, threshold variation may cause reliability problems for thin back-gate oxide DGFD SOI circuits operated at low supply voltage     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

A physically based compact device model for fully depleted andnearly fully depleted SOI MOSFET

A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device model suitable for analog as well as digital application has been proposed. It is an all region model. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, we have given careful consideration to parasitic source/drain resistance, Drain Induced Conductivity Enhancement (DICE) effect, floating body effect, self-heating and model continuity. A single parameter set is used for a large set of device dimensions except threshold voltage and parasitic source/drain resistance due to silicon film thickness variations. The accuracy of the model is validated with experimental data using NMOS FDSOI devices and found to be in good agreement     

Physical subthreshold MOSFET modeling applied to viable design ofdeep-submicrometer fully depleted SOI low-voltage CMOS technology

An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits     

Low frequency noise in fully depleted SOI PMOSFET's

Low frequency noise of fully depleted PMOSFET's on SOI substrates with various channel dopings was measured as a function of substrate-to-source bias. It was found that the device noise is a strong function of the substrate-to-source bias and a window exists in which the device noise is at its minimum. The position of the minimum noise region depends on the channel doping, and its width depends on the buried oxide thickness. Knowledge of the bias conditions under which the transistor will operate are necessary for proper selection of the channel doping for low noise PMOSFET design     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Fully depleted SOI MOSFET's include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentration's dependence on drain voltage     

High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs

In this paper, the electrical characteristics of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and a suppression of Negative bias temperature degradation in accumulation mode FD-SOI MOSFETs are described. Firstly, we experimentally demonstrate that the multi-gate MOSFETs using radical oxide effectively suppress the degradation of S-factor values resulted from its superior oxidation at the sidewall. Secondly, we indicate that the device performance is dramatically improved by introducing MUGFETs device structure originated from its effective channel area. Finally, we reveal the improvement of current drivability and a suppression of Negative bias temperature instability (NBTI) in accumulation mode FD-SOI MOSFETs.     

Carrier lifetime extraction in fully depleted dual-gate SOI devices

A new method for extracting the carrier recombination lifetime in dual-gate silicon-on-insulator (SOI) structures is proposed. The experiment, model, and numerical simulations indicate that an excess forward current is obtained when carrier recombination occurs in the whole film volume     

X-band fully depleted SOI Amplifier with adaptive bias control

A 10-GHz amplifier with an adaptive bias control circuit is realized using fully depleted SOI CMOS technology. The effective gate bias of the amplifier MOSFET adjusts itself based on the power level of the input signal. Measured results showed reduction of overall power consumption and wider range of output power near its peak efficiency. At absence of the signal, the amplifier can be automatically switched to a standby mode with approximately 85% reduction of power consumption. Power saving is also demonstrated for pulsed signal modulated at 10 MHz.     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies     

High-temperature and self-heating effects in fully depleted SOI MOSFETs

In this paper, the high-temperature and self-heating effects in the fully depleted enhancement lightly doped SOI n-MOSFETs are investigated over a wide range of temperatures from 300 to 600 °K by using the SILVACO¹ TCAD tools. In particular, we have studied their current-voltage characteristics (I_D-V_GS and I_D-V_DS), threshold voltages and propagation delays. Simulation results show that there exists a biasing point where the drain current and the transconductance are temperature independent. Such a point is known as the zero temperature coefficient (ZTC) bias point. The drain current ZTC bias points are identified in both the linear and saturation regions whereas the transconductance ZTC bias point exists only in the saturation region. We have observed that decreasing the film thickness could reduce the threshold voltage sensitivity of the SOI MOSFET with temperature and that the drain current decreases with increasing temperature. We have also noted that due to the self-heating effects, the drain current decreases with increasing drain bias exhibiting a negative conductance and that the self-heating effects reduced at a higher operating temperature. Self-heating effects are more pronounced for higher gate biases and thinner silicon films whereas the bulk device shows negligible self-heating effects.     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior