A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply     

A single-chip Si-bipolar 1.6-GHz VCO with integrated-bias network

A single-chip 2.7-V voltage-controlled oscillator (VCO) with an integrated-bias network has been implemented in an Si-bipolar process with an f_T of 25 GHz. With an on-chip resonator consisting of vertically coupled inductors and varactor diodes, an oscillation frequency of 1.56 GHz was measured. A careful design of the oscillator and bias network was necessary to achieve a phase noise performance of -139 dBc/Hz at 4.7 h MHz off carrier. The tuning sensitivity was 100 MHz/V, which is sufficient to compensate for production tolerances. The VCO can be used as a building block for single-chip transceivers in digital European cordless telephone or global system for mobile communication systems     

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

A 2-GHz Si-bipolar direct-conversion quadrature modulator with a wide bandwidth is described. It operates at a low supply-voltage of 2 V and features a “current-folded” double-balanced mixer with a two-stacked-transistor configuration, and a tunable RC/CR 90° phase shifter that reduces the amplitude imbalance and the phase error over a wide bandwidth (0.8 to 2 GHz). The modulator is implemented using 18-GHz Si-bipolar technology and dissipates only 68 mW at 2 V. The image ratio at 2 GHz is about -37 dBc, corresponding to a phase error of 1.6°. Moreover, both second-order and third-order products, and local signal leakage are less than -40 dBc     

A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm² and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

A 1.9-GHz single chip IF transceiver for digital cordless phones

A 1.9 GHz IF transceiver for the Japanese standard personal handy-phone system (PHS) is fabricated in a 0.8-μm BiCMOS process with 20 GHz npn. A down-mixer, up-mixer, variable attenuator, quadrature modulator, first and second PLL, and second VCO are included in the 3.4×3.0 mm² chip. The chip draws 24 mA in receive mode and 44 mA in transmit mode, operating from 3.0 V. A total vector error of 4% for the π/4 QPSK PN9 pattern includes the up-mixer and the dual PLLs     

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

A 1.9-GHz CMOS VCO with micromachined electromechanically tunablecapacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-μm CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 5.1-GHz 1.9-mW GaAs binary frequency divider

A GaAs divide-by-two circuit operating at a clock rate of 5.1 GHz and dissipating only 1.9 mW has been demonstrated. This represents the best room-temperature speed-power performance yet reported for any flip-flop. The D-type flip-flop owes its high performance to a 0.5-μm TiWN self-aligned gate fabrication process using low-capacitance dielectric material. The speed-power performance with this process is compared to other recent results for high-speed frequency dividers     

A variable 10.6-µ attenuator

A variable CO2laser attenuator with a dynamic range of 33 dB, large power handling capability, and reproducible attenuation has been constructed.     

A fiber connectorized MEMS variable optical attenuator

A voltage-controlled moving-mirror microelectro-mechanical systems variable optical attenuator is described that has less than 1-dB fiber-to-fiber insertion loss at 1550-nm wavelength and greater than 50-dB dynamic range. The device was configured with a simple feedback circuit to operate as an optical power regulator capable of stabilizing the output power to within 0.26 dB for a 12-dB input power excursion     

A very thin power amplifier multichip module for 1.9-GHz cellularphone systems

A compact thin power amplifier module for 1.9-GHz cellular phone systems has been incorporated using MCM-D technology and planarization technology of all passive components. The module consists of four Si-MOSFETs and is 9.4×7.2×1 mm, resulting in a volume of 0.07 cc including its shield metallic case. The module was designed with the computer simulator, Libra, and simplified lumped-element equivalent circuits of passive components. The fabricated module exhibited an output power of 33.3 dBm and power efficiency of 29%. These results suggest that these technologies will be very useful for the miniaturization of circuit components for GHz-band mobile communications     

A 1.9-GHz, 1-W CMOS class-E power amplifier for wirelesscommunications

This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-μm CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun)     

A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications

The design of a radio-frequency transmitter that can operate in two bands while employing a minimal number of external components entails many challenges at both the architecture and the circuit levels. This paper describes the design of a 900-MHz/1.8-GHz transmitter implemented in CMOS technology for dual-band applications. Configured as a two-step architecture, the circuit generates the first upconverted signal in quadrature form and subsequently performs single-sideband modulation to produce the output in two bands. Fabricated in a 0.6-μm digital CMOS technology, the transmitter exhibits unwanted spurs 40 dB below the carrier while drawing 75 mW from a 3-V supply     

A novel, linear voltage variable MMIC attenuator

Voltage variable attenuators (VVAs) for microwave applications that are fabricated using present technology and design methods feature a nonlinear relationship between the attenuation measured in decibels and the control signal. A novel VVA that features a linear attenuation-control-voltage relationship without the need for external linearization is described. This is accomplished by connecting a number of FET segments in a unique fashion to form a composite FET. The channel resistance of the composite FET constitutes a prescribed function of its gate-source voltage. By careful design the resistance functions that are necessary for realization of linear attenuators are synthesized. The attenuator was fabricated using GaAs MMIC technology employing MESFETs as voltage variable resistors. It is completely passive and does not require a DC supply. The attenuation ranges from 2 to 15 dB over DC to 8 GHz while port impedance is kept close to 50 Ω. The deviation of the attenuation from a straight line is less than 0.2 dB     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.