基于MESFET非线性模型的MOSFET DC建模技术

常用的MOSFET模型模型参数多且复杂,在保证精确度的基础上应尽量简化模型。尝试采用目前比较成熟通用的MESFET非线性等效电路经验模型表征射频MOSFET的直流特性。进行模型参数提取,从模型对MOSFET的DC仿真与测量曲线数据的对比结果,以及采用这6个模型仿真MOSFET直流特性时的RMS误差结果来看,这6个常用的MESFET非线性模型可以表征MOSFET的直流特性,参数越多模型精度越高。     

3 nm环栅场效应管射频小信号等效电路模型

针对3 nm环栅场效应晶体管,提出了一种射频小信号等效电路模型及基于有理函数拟合的解析模型参数提取方法。首先,在关态条件下提取不受偏置影响的非本征栅/源/漏极电阻、栅到源/漏电容、衬底电容和电阻。然后,在不同偏置条件下提取受偏置影响的本征模型参数。使用Sentaurus TCAD和Matlab对器件进行仿真并拟合得到相关参数,在ADS中验证等效电路模型。结果表明,在10 MHz~300 GHz频率范围内,TCAD仿真与等效电路仿真S参数的最大误差低于2.69%,证实了所建立模型及建模方法的准确性。该项研究成果对射频集成电路设计具有参考价值。     

一个适用于RFIC设计的RF MOSFET源漏电阻可缩放模型

提出了一个可用于0.18 μm CMOS工艺RF-MOSFET的源漏电阻的可缩放模型.采用了一种直接基于S参数测量的方法来准确提取端口的寄生电阻,该模型充分考虑了各种版图尺寸,如沟道长度,沟道宽度和栅极指头数目等参数的可缩放性.此后,该模型通过不同尺寸的共源连接RF MOSFET的测量和仿真的直流、小信号S参数特性比对,曲线达到了较好的吻合,表明我们的模型是精确而且有效的.     

基于表面电势的高压LDMOS晶体管直流模型改进

针对标准MOSFET的BSIM3和PSP模型在高压LDMOS建模上的不足,提出了基于PSP表面电势方程的改进高压LDMOS晶体管I-V模型.在研究过程中,使用Agilent系列直流测试设备及ICCAP参数提取软件和ADS仿真器对高压LDMOS晶体管进行数据采集及参数提取.在开放的PSP模型Verilog-A代码基础上完成改进代码的实现.最终的结果表明,采用改进后的模型,仿真曲线与测量的I-V曲线十分吻合,该模型大大提高了PSP I-V模型模拟高压LDMOS晶体管时的精确度,对于实用高压集成电路的设计和仿真有着重要意义.     

基于非线性电阻的GaN HEMT经验基大信号模型

为了实现建立准确的氮化镓高电子迁移率晶体管（GaN high electron mobility transistor,GaN HEMT）大信号模型的目的,提出了一种基于非线性电阻的GaN HEMT经验基大信号模型. 通过对GaN HEMT在高漏极偏置和高电流密度下的电阻特性分析,将受漏源电流控制的非线性电阻模型嵌入经验基大信号模型中. 结合Matlab和ADS提取模型初值,在ADS中建立完整的大信号符号定义模型. 选择栅长为0.25 μm,栅宽分别为2×200 μm、2×250 μm、4×200 μm的GaN HEMT进行直流输出特性和大信号输出特性仿真验证,结果表明本文模型与测试数据具有较高的吻合性. 该大信号模型提高了经验基大信号模型的物理特性,具有较高的精度及良好的缩放性.     

高压集成电路中的HV MOS晶体管BSIM3 I-V模型改进

针对SPICE BSIM3模型在对大量应用于高压集成电路中的轻掺杂漏高压MOS(简称HV MOS)晶体管建模上的不足,提出了基于BSIM3的高压MOS晶体管I-V模型改进.研究中使用Agilent ICCAP测量系统对HVMOS晶体管进行数据采集,并分析其源漏电阻受栅源、源漏和衬底电压的影响及与标准工艺低压MOS晶体管的差异,针对BSIM3模型源代码中源漏电阻R ds的相关参数算法进行了改进,保留BSIM3v3原有参数的同时增加了R ds的二次栅压调制因子Prwg2和有效Vas参数δ的栅压调制因子δ1,δ2,在开放的SPICE和BSIM3v3源代码上对模型库文件进行修改并实现了优化.仿真结果表明采用改进后的模型,在ICCAP下的测量曲线与参数提取后的I-V仿真曲线十分吻合,该模型大大提高了BSIM3 I-V模型模拟HV MOS晶体管时的精确度,对于高压集成电路的设计与仿真有着极其重要的意义.     

高压集成电路中的HV MOS晶体管BSIM3 I-V模型改进

针对SPICE BSIM3模型在对大量应用于高压集成电路中的轻掺杂漏高压MOS(简称HV MOS)晶体管建模上的不足,提出了基于BSIM3的高压MOS晶体管I-V模型改进.研究中使用Agilent ICCAP测量系统对HVMOS晶体管进行数据采集,并分析其源漏电阻受栅源、源漏和衬底电压的影响及与标准工艺低压MOS晶体管的差异,针对BSIM3模型源代码中源漏电阻R ds的相关参数算法进行了改进,保留BSIM3v3原有参数的同时增加了R ds的二次栅压调制因子Prwg2和有效Vas参数δ的栅压调制因子δ1,δ2,在开放的SPICE和BSIM3v3源代码上对模型库文件进行修改并实现了优化.仿真结果表明采用改进后的模型,在ICCAP下的测量曲线与参数提取后的I-V仿真曲线十分吻合,该模型大大提高了BSIM3 I-V模型模拟HV MOS晶体管时的精确度,对于高压集成电路的设计与仿真有着极其重要的意义.     

射频场效应晶体管的交流小信号建模技术研究

提出了新的金属-氧化层-半导体-场效晶体管（MOSFET）器件的小信号等效电路结构,提取了等效电路结构的元件参数值,在器件建模型软件IC-CAP2008下,对等效电路模型和提取的元件参数进行编译,生成了能够应用于射频与微波领域的场效应晶体管的高频小信号器件模型,将生成的器件模型编译到高频仿真软件ADS中,并调用S参数仿真器对器件模型进行S参数仿真,最后对比了仿真结果与测试数据的差异性,对生成的器件模型做出了误差分析,展示了所建小信号模型的良好性能。     

尺寸可变的65nm多叉指射频CMOS器件模型提取与优化

通过对CMOS PSP直流核心模型进行STI参数的修正、探针电阻的引入和提取以及尺寸可变的源漏寄生电阻表达式的引入,呈现了一个尺寸可变的65 nm多叉指射频CMOS器件模型及其提取和优化方法.与实验数据比较结果表明,该模型及其提取和优化方法能够在14 GHz以内精确地预测器件性能.     

短沟道MOSFET源漏寄生电阻的二维半解析模型北大核心CSCD

根据金属氧化物半导体场效应晶体管(MOSFET)的工作原理,在MOSFET的源/漏区域引入了矩形等效源,提出了源/漏电阻的二维定解问题。通过用分离变量法、傅里叶展开和积分方程相结合建立MOSFET源/漏电阻的二维半解析模型,得到了源/漏电阻与几何尺寸之间的关系。该模型避免了数值分析时的方程的离散化,且具有较高的精度。计算和仿真结果表明,模型计算出的源/漏电阻阻值接近于Silvaco的仿真值。     

GaAs MESFET非线性CAD模型综述

介绍了ＧａＡｓＭＥＳＦＥＴ应用在商业软件中的四种非线性ＣＡＤ模型、ＰＳＰＩＣＥ程序中的ＳＴＡＴＺ模型、ＥＥｓｏｆ微波电路模拟程序中的Ｃｕｒｔｉｃｅ对称和不对称模型以及ＱＵＡＳＩ程序中改进的ＳＴＡＴＺ模型。在给出多种模型ＤＣ方程和源漏电容公式的同时，对三种电路模拟程序的应用范围进行了分析。     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET

In this paper, for the first time, we have analyzed DC characteristics and analog/RF performances for nanowire quadruple-gate (QuaG) gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET), using isomorphic polynomial function for potential distribution. The QuaG GAA MOSFET not only suppresses the short channel effects (SCEs) and offer ideal subthreshold slope (SS), but also is a good candidate for analog/RF device due to its high transconductance (g_m) and high cutoff frequency (f_T). Therefore, this work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. For this, the developed model is based on the solution of 3D Laplace and Poisson׳s equations for subthreshold and strong inversion regions respectively. The developed potential model has been used to formulate a new model for total gate, drain and source charge. Further, the expression for different capacitance for investigating RF performance is obtained from the developed model. Finally, the developed device electrostatics for QuaG GAA MOSFET have been used for the analysis of analog/RF performance. Different capacitances and analog/RF figures of merit are extracted from small signal frequency (1 MHz) ac device simulation. Whereas technology computer-aided design (TCAD) simulations have been performed by 3D ATLAS, Silvaco International.     

一种改进的深亚微米MOSFET噪声模型

提出一种基于小信号的噪声模型,在精确提取0.13 μm MOSFET的小信号参数后,结合Pospieszalsik和pucel模型,运用噪声相关矩阵转换技术提取出所有噪声参数。利用ADS建立噪声模型,在2～20 GHz频率范围内,仿真结果与测量结果吻合良好,验证了模型的准确性。     

A new empirical nonlinear model for sub-250 nm channel MOSFET

An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which is useful for large signal RF circuit simulation. Our model is made of both analytical drain current and gate charge formulations. The drain current expression is continuous and infinitely derivable, and charge conservation is taken into account, as the capacitances derive from a single charge expression. The model's parameters are first extracted, prior the model's implementation into a circuit simulator. It is validated through dc, ac, and RF large signal measurements compared to the simulation.     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

Precise macromodel applied to high-voltage power MOSFET

A macromodel for precise simulations of high-voltage power MOSFET is presented. The macromodel takes into account basic features of these devices as higher value of the resistance between channel and drain and lower current level though the body diode compared to low-voltage power MOSFET. It also considers that high-voltage power MOSFET work mostly in saturation regime. All required parameters are extracted from direct electrical measurements. Simulations using this and previous macromodels are compared with experimental DC and AC characteristics to demonstrate a much better correspondence with experiment of the macromodel presented.