一种用于流水线结构ADC中改进速度/功耗比的CMOS动态比较器

提出了一种适用于高速、单级低分辨率流水线结构ADC的全差分动态比较器.由于采用了电流源耦合和差分对输入结构,比较器的翻转阈值电压可以设计为任意值.与传统的比较器相比,该比较器较好地兼顾了面积、功耗以及速度等方面,在这些方面有了较大的改进.该比较器在0.35μm CMOS工艺下完成流片,面积为30μm×70μm.仿真和测试结果表明,该比较器可以在2Vpp的输入信号和1GHz的时钟频率下工作,在3.3V的电源电压下,功耗仅为181μW.速度/功耗比达到了5524GS/J.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter

This paper presents a comparator generation and selection method to reduce the linearity errors—DNL and INL—for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2 ⁿ – 1 comparators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different sizes to provide internal reference voltages, while the differential comparators have identical sizes. The design method has been incorporated into a software package and the 2 ⁿ – 1 optimized TIQ comparator layouts are generated as an output of the software package. The linearity errors against the CMOS process, power supply voltage, and temperature variations are significantly improved by the proposed comparator generation and selection method for the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation can be almost eliminated. The simulation results show 82.6% of DNL and 32.5% of INL improvements against CMOS process variation. For the other variations—power supply voltage and temperature—43.5% for DNL and 6.0% for INL improvement has been achieved. The prototype chips have been fabricated and the chip test results confirms the simulation results.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

A low-power low-offset dynamic comparator for analog to digital converters

A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive Monte-Carlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180 nm and 90 nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators.     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

High performance CMOS current comparator

A new high-speed CMOS current comparator is described. By changing the buffer of an existing comparator from class B to class AB operation, voltage swings are reduced, resulting in greater speed for small input currents. Simulation results employing a 1.6μm CMOS technology show the response time to a 0.1μA input current to be 11ns and the power dissipation to be 1.4mW, resulting in a five times improvement in speed/power ratio over existing high-speed current comparators     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

Low-power 600MHz comparator for 0.5V supply voltage in 0.12 lm CMOS

A comparator, fabricated in a 1.5 V/0.12 mum CMOS process, is presented. The commonly separated reset and active-load transistors of typical comparators are combined. In the input part two NMOS transistors are added to reduce power consumption. At a supply voltage of 0.5 V the comparator works at a maximal clock of 600 MHz and consumes 18 muW     

Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compensated for by calibration, noise can irreparably hinder performance and is less straightforward to be accounted for at design time. This paper presents a method to estimate the input referred noise in fully dynamic regenerative comparators leveraging a reference architecture. A time-domain analysis is proposed that accounts for the time varying nature of the circuit exploiting some basic results from the solution of stochastic differential equations. The resulting symbolic expressions allow focusing designers' attention on the most influential noise contributors. Analysis results are validated by comparison with electrical simulations and measurement results from two ADC prototypes based on the reference comparator architecture, implemented in 0.18- $mu{hbox {m}}$ and 90-nm CMOS technologies.      

A fully differential comparator using a switched-capacitordifferencing circuit with common-mode rejection

A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-μm CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-μm CMOS process, the comparator occupies 0.25 mm² and dissipates 1.05 mW     

基于Latch的CMOS动态比较器的研究

动态比较器具有高速和低功耗的优点,是现代集成电路中的重要单元。本文简单介绍了基于latch的CMOS动态比较器的基本工作原理以及国内外最新研究进展;分析了几种新型动态比较器的性能。     

一种高电源效率开关电流比较器

提出了一种基于Boonsobhak结构但电源效率更高的开关电流比较器。比较器采用主从式结构,工作模式由两相不交叠时钟控制。主比较器根据输入电流信号的极性产生微小电压差,同时将输出信号对输入信号的影响隔离开来。从比较器将主比较器产生的微小电压差进行再生放大,最终产生比较结果。提出的新比较器结构采用静态甲乙类锁存式比较器作为主比较器,以静态功耗为零的动态锁存式比较器为从比较器,使得整体比较器在保持较高速度的同时,功耗大为降低。采用CSMC0.6μmCMOS工艺设计并实现,实际测试结果显示开关电流比较器具有6.5bit分辨率,能在20MHz时钟频率下正常工作,而功耗降低了75%。     

A high-speed,high fan-in dynamic comparator with low transistor count

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time.     

A 0.5?V high-speed comparator with rail-to-rail input range

A 0.5?V high-speed comparator with rail-to-rail input range is presented. Unlike conventional rail-to-rail comparators that use both NMOS and PMOS input devices, the proposed design takes advantage of zero-V _t NMOS devices that are available in many CMOS processes tailored for analog and mixed signal applications. Design issues associated with the use of zero-V _t devices in comparator circuits are analyzed. Based on a 0.13???m CMOS technology, the proposed design is compared with recently reported sub 1?V comparators and it shows significant performance improvement by the proposed design.     

A mux-based High-Performance Single-Cycle CMOS Comparator

In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%.     

一种新型低功耗异步比较器的设计方法

本文利用输入数据的统计特性,设计了两种低功耗异步比较器——异步行波比较器和提前终止异步比较器.异步行波比较器从第一个不相等的数位开始停止运算,但要把结果传到最低位,消耗部分功耗.提前终止异步比较器通过修改真值表,基于新的比较单元电路和终止判断电路,在第一个不相等的数位停止运算并立即输出比较结果,节省不必要的功耗.新设计的异步比较器和用于对比的同步比较器(BCL比较器和门控时钟比较器)均用SMIC0.18μm工艺实现.仿真结果表明,提前终止异步比较器功耗最低,与同步BCL比较器和门控时钟比较器相比,在随机数据和来自LDPC解码器的数据下,分别节省了87.1%、84.5%和37.5%、28.6%的功耗.     

一种高速开关电容动态锁存比较器分析与设计

设计了一种基于CMOS工艺的开关电容动态锁存比较器。该比较器包含一个共模不敏感全差分开关电容采样级和一级动态锁存比较器。开关电容采样级验证了比较器的输入共模范围,动态锁存器采用两个正反馈锁存器和额外的反馈环路提高了锁存的速度。基于0.18μm 1.8V CMOS工艺进行了版图设计和后仿真,结果表明该比较器可以应用于200 MSPS高精度流水线模数转换器。     

CMOS Latch Using Quad for High-Speed Comparators

The well-known CMOS quad consisting of two asymmetric differential pairs is a transconductance element. It provides an additional output current proportional to the square of its differential input voltage. Here, we use both the linear and square-law outputs of a quad to build a high-speed latch that has differential low-voltage output swing. This latch retains the useful property of constant power-supply current like all current-biased differential current-mode logic circuits. Simulation results for 0.18-mum CMOS process are presented. The design is application specific and is intended for use in high-speed comparators needed for analog-to-digital converters