基于电流环路控制方法的快速响应LDO

LDO电路的瞬态响应能力是评价LDO性能的一个重要指标。本文借鉴电荷泵式锁相环的环路控制方法,提出了一种基于电流控制环路的LDO结构,将典型LDO电路中的电压比较改为电流比较,利用跨导放大器和环路滤波器产生功率管的控制栅压,使得环路具有优化的阻尼因子ζ和固有频率ωn,有效提高了LDO环路的瞬态响应能力,并且输出电压可以低至1V以下,且不受基准电压的限制。基于0.13μm CMOS工艺的实现结果表明,在使用1μF去耦电容,LDO输出1.0V的情况下,负载100μA→100mA瞬态变化时,输出超调5.11mV,稳定输出的压降4.25mV,稳定时间8.2μs,而负载100mA→100μA时,输出超调6.21mV,稳定输出的压降4.25mV,稳定时间23.3μs。结果表明,该电路各项性能指标均有明显的提高,FOM指数达到0.0097。     

应用动态偏置和双环反馈技术的CMOS快速瞬态响应低压差线性稳压器设计

This paper presents a low-dropout regulator （LDO） for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59~ phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113μA. The line regulation and load regulation are improved to 0. l mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

一种应用平行反馈补偿和瞬态响应增强技术的NMOS低压差电压调整器设计

本文提出了一种应用于便携式设备的,采用平行反馈补偿和瞬态响应增强技术的低压差电压调整器。平行反馈的架构引入了一个动态零点,保证环路在0A到1A的负载电流范围内具有足够的相位裕度。通过采用Class-AB结构的误差运放和快速充放电单元增强系统的瞬态响应能力。本文提出的低压差电压调整器采用0.35μm BCD工艺制造。测试结果显示,稳压器的静态电流为165μA,在1A满载情况下,压差可以达到150mV。在满负载瞬态跳变时,输出电压下掉和过冲幅度分别降低到38mV和27mV。     

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and I_Q of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.     

A 3 A sink/source current fast transient response low-dropout Gm driven linear regulator

A 3 A sink/source G_m-driven CMOS low-dropout regulator(LDO),specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m(transconductance)driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm~2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.     

A novel dual-feed low-dropout regulator

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.     

A high precision low dropout regulator with nested feedback loops

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is and 20 in parallel.     

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip (SoC) requires multiple integrated voltage regulators with a small area, process scalability, and low supply voltage. Conventional on-chip analog low-dropout regulators (ALDOs) can hardly meet these requirements, while digital LDOs (DLDOs) are good alternatives. However, the conventional DLDO, with synchronous control, has inherently slow transient response limited by the power-speed trade-off. Meanwhile, it has a poor power supply rejection (PSR), because the fully turned-on power switches in DLDO are vulnerable to power supply ripples. In this comparative study on DLDOs, first, we compare the pros and cons between ALDO and DLDO in general. Then, we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement. Finally, we discuss the design trends and possible directions of DLDO.     

一款灌入/拉出3A电流跨导驱动快速瞬态响应低漏失稳压器

本文设计了一款可以灌入(sink)和拉出(source)3A电流,低电源、低功耗的CMOS低漏失电压线性稳压器。采用电流镜像结Gm(跨导)驱动的LDO架构可以获得高稳定性和快速负载瞬态响应。基于UMC 0.5um标准CMOS工艺投片验证,芯片面积为1.0mm2。空载时该LDO静态电流为220uA,最大带载3A。测试表明,使用30uF陶瓷电容,在-1.8A到 1.8A 0.1us负载跳变时,该LDO可以在低于2us的时间达到稳态,且过冲小于1mV。     

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90 nm CMOS process is only 0.054 mm². Experimental results show that the developed LDO can supply up to 15 mA and it presents a very fast transient response, with a settling time of approximately 30 ns and a voltage drop of 200 mV when the load current changes from 100 nA to 9 mA.     

全光网中功率放大器瞬态响应的消除

对光网络中ＥＤＦＡ的瞬态响应产生的原因进行了并对相关因素进行了实验。提出了自己的解决方案,并对方案进行实验论证,取得了预想的效果。     

一种1.8伏带有foldback过流过热保护的低压线性稳压器设计

This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.     

A 1.8 V LDO voltage regulator with foldback current limit and thermal protection

a drop-out voltage of 200 mV at a maximum load current of 240 mA.     

A fixed frequency fast transient response DC-DC controller for VRM application Chen Mingyang(陈明阳), Zhao Menglian*(赵梦恋), Wu Xiaobo(吴晓波)

A 2V-10A fast transient response DC-DC buck controller based on fixed frequency hysteresis control is presented. A carefully designed output voltage filter detects the output capacitor current change which helps the controller to respond immediately after load changes. Adaptive hysteresis control guarantees the switching frequency to be the same as the reference frequency by using a CCII-composed circuit and current mirrors. The controller is designed and fabricated in a TSMC 0.35 μm process. Simulation and test results show that this con- troller achieves a 20 μs settling time in one single switching cycle when load current changes from 1 A to the full load condition at 10 A.     

一种分高低压供电的低压差线性稳压器的设计

针对传统低压供电的低压差线性稳压器线性响应比较慢的情况,提出了一种基于BICMOS 0.5μm工艺分高低压供电的低压差线性稳压器。经过Hspice仿真验证,该稳压器具有高增益、高PSRR（Power Supply Rejection Ratio,电源抑制比）、低功耗、响应速度快的特点,输入电压范围为0.5~28.0 V,输出电压为5 V。此稳定器低频时的开环增益达到86 dB,相位裕度为68o,低频时的电源电压抑制比为–91 dB,高频时也能达到–2 dB,静态电流只有13.5μA。     

Bidirectional DC resonant converter with magnetic-coupling current balance

This paper studied a bidirectional frequency-control dc converter with magnetic-coupling to achieve 1) current balance on low voltage side, 2) low switching losses on power devices, and 3) bidirectional power transfer capability. The developed circuit is basically constructed by half-bridge circuits on input and output sides. LLC resonant tank with frequency-control is used to obtain low switching losses on power devices. Magnetic-coupling element is used to achieve current balance on low voltage side. Synchronous rectifiers are employed on low voltage and high current side to decrease power losses and increase circuit efficiency. The effectiveness of the studied circuit is verified from a 720 W laboratory prototype.     

一种无片外电容的快速响应FVF-LDO北大核心

提出了一种无片外电容、快速瞬态响应、宽输入电压范围的低压差线性稳压器(LDO)。该电路基于翻转电压跟随器(FVF)结构，不需额外增加辅助电路，仅使用两个电容作为检测模块，以动态调整瞬态响应，能够弥补传统LDO集成度低、面积大、功耗高、瞬态响应差的不足。电路基于TSMC 180 nm CMOS工艺。仿真结果表明，该LDO的压差为200 mV,静态电流为36μA,输入电压范围为2～4 V,低频时PSRR为-59 dB。在30 pF负载电容、0～10 mA负载电流、150 ns阶跃时间条件下，产生的上冲电压为50 mV,下冲电压为66 mV,瞬态电压恢复时间为300 ns。     

一种快速瞬态响应的无片外电容型LDO

设计了一种快速瞬态响应的无片外电容型LDO。采用高增益高带宽的超级跨导结构(STC)的误差放大器,利用动态偏置技术与电容耦合技术,极大地增强了摆率。引入额外的快速响应环路,进一步提升了瞬态响应速度。基于0.18 μm CMOS工艺进行设计。结果表明,该LDO的最低供电电压为1 V,漏失电压仅为200 mV,可提供最大100 mA的负载电流,能在最大输出电容为100 pF、最低负载为50 μA的条件下保证电路稳定。负载电流在0.5 μs内由50 μA跳变至100 mA时,LDO输出导致的过冲电压和下冲电压分别为200 mV和306 mV。     

基于平均电流的双闭环APFC电路的设计

为有效消除电力电子设备的谐波干扰,基于UC3855设计了BOOST功率因数校正电路。主电路为减少功率损耗采用ZVT零电压辅助开关。控制电路采用双闭环平均电流模式。利用乘法器校正使输入电流接近正弦波并保持与电压同相位。通过小信号建模推导了电流环、电压环传递函数,配置了系统双环补偿校正网络的参数。最后通过MATLAB仿真和实验验证了设计的正确性。系统的动、稳态性能良好,功率因数接近为1。