Ka波段镜像抑制谐波混频器设计

针对现代毫米波接收机和雷达系统高抗干扰能力的需求,分析了具有镜像频率抑制能力的谐波混频器的基本原理,提出了一种Ka波段镜像抑制谐波混频器的设计方案。该混频器由两个混频单元组成,利用输出信号的相位关系识别RF信号和镜频信号,RF混频信号在输出端口同相叠加,镜频混频信号反相抵消。使用Ansoft HFSS和Agilent ADS仿真软件分别完成电路无源部分仿真和谐波平衡仿真设计,制作了混频器并进行了测试。测试结果表明:RF频率为29.4～31GHz,中频(IF)为100 MHz,变频损耗稳定在8.8～10.3 dB,镜像抑制度大于20.1 dB,各个端口隔离度均大于31.4 dB,RF端口和本振(LO)端口驻波比分别小于1.3和2.2,输入功率在1 dB压缩点为-5 dBm。     

无源正交混频器HMC620LC4的原理与应用

HMC620LC是基泰尔微波公司推出的一款紧凑型正交混频器.该芯片由双平衡混频器、3dB耦合器(90°移相)构成,利用砷化镓MESFET工艺制作.该芯片具备宽中频输出,本振到射频端口隔离度高,镜频抑制能力优越,幅度和相位平衡出色,可用作镜频抑制混频器.介绍了HMC620LC4芯片的器件特性与结构.以及器件工作的基本原理.最后,将该器件作为下变频组件应用在0～2GHz的幅相检测系统中,对射频器件能够实现简单的幅相测量.     

一种基于0.18-μm CMOS 工艺的超宽频带分布式无源栅注入混频器

本文介绍了一种基于0.18-μm CMOS 工艺的宽带无源分布式栅注入混频器。通过采用分布式拓扑结构,该混频器具有很宽的工作频带;中频输出端口使用了一个4阶低通滤波器,从而极大地提高端口之间的隔离度。此外,文中还分析了混频器的阻抗匹配与转换损耗。测试表明：该混频器在3GHz到40GHz频率范围工作时的转换损耗为 9.4 ~ 17 dB,零直流功耗,其芯片面积为0.78 mm2。在射频频率为23GHz固定中频频率为500MHz时的输入参考1dB压缩点大于4dBm。在整个工作频带内,其射频到本振端口、射频到中频端口及本振到中频端口的隔离度分别大于21dB, 38dB,45dB。该混频器适用于WLAN,UWB,Wi-Max,车载雷达系统和其它毫米波射频的相关应用。     

Ka波段三路波导功分器/合路器

文章设计了一种可以使用在固态合成发射机上的三路等分功率波导功分器/合路器。在波导分支定向耦合器的基础上,增加一路副线波导,构成了一个一路输入、一路直通、两路耦合、两路隔离的六端口网络;采用增加波导长度的方式解决了实际应用中的相位补偿问题。另外在功分器的三路输出端增加了微带部分以提高功分器的可调试性。实际测量数据基本符合仿真结果:在1GHz带宽内,功分器的一路插损小于6dB,输入驻波小于1.6;合路器的一路插损小于4.9dB,输出驻波小于1.3。其性能满足使用要求。文章最后对该类型的波导功分器/合路器的设计提出若干改进方案。     

基于微带无源电路的宽带毫米波分谐波混频器（英文）

设计了一款基于微带结构的宽带毫米波分谐波混频器。混频器中引入了短路结构的宽带射频滤波器以及一个高性能本振-中频双工器,这些无源电路能够抑制空闲组合频率,同时为中频、射频以及本振信号提供合适的回路。测试结果表明,本文设计的毫米波分谐波混频器射频工作频率为27～48 GHz,中频工作频率宽至6 GHz.在整个工作频段内上、下变频损耗均小于12.5 dB。当射频为33 GHz,中频为1 GHz时,上变频、下变频达到最小变频损耗分别为8.2 dB和7.5 dB。     

Ka频段宽带镜频抑制谐波混频器的设计

介绍了一种在Ka频段具有镜频抑制功能的四次谐波混合集成电路混频器的设计与实现.该混频器主要采用微带混合集成电路,由薄膜陶瓷基片制作.经测试,当中频固定在70 MHz,在射频大于4 GHz带宽内,变频损耗小于11.2 dB,镜频抑制度大于20 dB.     

0.1 THz鳍线单平衡式基波混频电路研究

研究了一种基于石英基片的0.1 THz频段的鳍线单平衡混频电路,混频电路的射频和本振信号分别从WR10标准波导端口通过波导单面鳍线微带过渡和波导微带探针过渡输入,中频信号通过本振中频双工器输出。这是一种新型的混频电路形式,与传统的W波段混频器相比,混频电路可以省略一个复杂的W波段滤波器,具有电路设计简单、安装方便的特点。该电路使用两只肖特基二极管通过倒装焊工艺粘结在厚度为75 m的石英基片上,石英基片相对传统基板,可以极大提高电路加工精度。在固定50 MHz中频信号时,射频90~110 GHz范围内,0.1 THz混频器单边带变频损耗小于9 dB。     

120 GHz GaAs MMIC双平衡式基尔伯特混频器

作为低频段混频电路中的典型拓扑结构,基尔伯特单元在毫米波、太赫兹领域的应用较少,在Ⅲ-Ⅴ族化合物半导体单片微波集成电路(MMIC)设计中,超过100 GHz的基尔伯特混频器很少有文献报导。基于70 nm GaAs mHEMT工艺,设计了一款120 GHz的双平衡式基尔伯特混频器,同时对该混频器版图结构进行优化改进,提升了混频器中频差分输出端口间的平衡度。仿真结果显示该混频器在本振输入0 dBm功率时,在100~135 GHz频率范围内有(-7.6±1.5) dB的变频损耗,射频输入1 dB压缩点为0 dBm@120 GHz,中频输出带宽大于10 GHz,差分输出信号间的功率失配<1 dB,相位失配<4°。该芯片直流功耗为90 mW,面积为1.5 mm×1.5 mm。     

4～8GHz GaAs HBT单片双平衡混频器

介绍了一种基于 GaAs HBT 的双平衡混频器.该混频器将射频、本振有源Balun集成其中,在RF和LO输入端分别采用不同的LC网络实现宽带的阻抗匹配.跨导级和开关单元之间采用交流耦合,并通过带宽扩展技术实现频带内的增益平坦.测量结果显示,该混频器匹配良好,射频端口S11在3～10 GHz频带内小于-10 dB.在固定中频200 MHz 情况下测试,在4～8 GHz射频频带内,平均增益10 dB,波动小于1 dB,中频输出端口对射频信号的隔离度优于25 dB,对本振信号的隔离度优于28 dB;本振-射频端口隔离度优于32 dB.在3.3 V直流电压下测得的功耗为66 mW.     

用于数字相控阵雷达收发组件的0.7~4.0GHz SOI CMOS有源下混频器

基于0.18μm SOI CMOS工艺设计了一款用于数字相控阵雷达的宽带有源下混频器。该混频器集成了射频、本振放大器、Gilbert混频电路、中频放大器以及ESD保护电路。该芯片可以直接差分输出,亦可经过片外balun合成单端信号后输出。射频和本振端口VSWR的测试结果在0.7~4.0GHz范围内均小于2,IF端口的VSWR测试结果在25 MHz~1GHz范围内小于2。当差分输出时,该混频器的功率转换增益为10dB,1dB压缩点输出功率为3.3dBm。电源电压为2.5V,静态电流为64mA,芯片面积仅为1.0mm×0.9mm。     

A 28-GHz SiGe up-conversion mixer using a series-connected triplet for higher dynamic range and improved IF port return loss

This work presents a fully integrated SiGe microwave up-conversion mixer, utilizing a new circuit topology consisting of a common-base, series-connected triplet at the IF port to achieve a significant improvement in dynamic range. This circuit functions with an IF signal of 1.25 GHz, and has an input 1-dB compression point (IP/sub 1dB/) of -6.8 dBm, for an RF output at 28 GHz. The circuit operates over a frequency range from 19 to 31 GHz, with a maximum conversion gain of 1 dB. The mixer can operate over an IF range from 1 to 10 GHz, while maintaining an IF port return loss greater than 10 dB.     

Architecture and algorithm for ultra-high precision image rejectionmixer using digital compensation

A Weaver-type ultra-high precision image rejection RF mixer architecture composed of analogue RF and digital IF mixers is proposed, along with the error compensating algorithm for various gain and phase mismatches. A prototype 2.4 GHz image rejection mixer using this technique with an image rejection ratio >70 dB is demonstrated     

InAlAs/InGaAs HBT X-band double-balanced upconverter

We report on an InAlAs/InGaAs HBT Gilbert cell double-balanced mixer which upconverts a 3 GHz IF signal to an RF frequency of 5-12 GHz. The mixer cell achieves a conversion loss of between 0.8 dB and 2.6 dB from 5 to 12 GHz. The LO-RF and IF-RF isolations are better than 30 dB at an LO drive of +5 dBm across the RF band. A pre-distortion circuit is used to increase the linear input power range of the LO port to above +5 dBm. Discrete amplifiers designed for the IF and RF frequency ports make up the complete upconverter architecture which achieves a conversion gain of 40 dB for an RF output bandwidth of 10 GHz. The upconverter chip set fabricated with InAlAs/InGaAs HBT's demonstrates the widest gain-bandwidth performance of a Gilbert cell based upconverter compared to previous GaAs and InP HBT or Si-bipolar IC's     

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8–11 dB over a wide RF frequency range of 9–31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12–15dB over an RF frequency range of 6.5–20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12–15dB within an RF frequency range of 12–33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.     

Millimeter-Wave Lange Coupler Design and Its Application in the Monolithic Image Rejection Mixer Design

This paper reports on the design of a Ka-band monolithic Lange coupler and its application in the monolithic fourth-harmonic image rejection mixer. Detailed design and analysis using Ansoft-HFSS simulator have been carried out. The simulated results of the Lange Coupler show the insert loss is better than ?3.64 dB; the amplitude balance is less than 0.55 dB and the phase balance is less than 0.65° from the 90° phase difference over the 30 to 40 GHz frequency range. The Lange Coupler is employed in a monolithic image rejection mixer that is fabricated by a commercial 0.18-μm pseudomorphic high electron-mobility transistor (pHEMT) process. The chip size is 1.4 mm × 1.9 mm. The image rejection ratio (IMR) is from 15 to 34 dB in the RF frequency range of 30 to 40 GHz.     

Design of Ka-band Monolithic Image Rejection Mixer

In this paper, a 30–40 GHz monolithic image rejection mixer is described. The mixer employs two drain LO injection mixer cells, which can perform well even with zero drain bias voltage. Also it employs Lange Coupler for RF quadrature signal generation. The mixer is fabricated by a commercial 0.18-μm pseudomorphic high electron-mobility transistor (pHEMT) process. It achieves image rejection ratio of more than 20.4 dB and conversion loss of less than 12.6 dB in the frequency range of 30 to 38 GHz.     

A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25 GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than ?10 dB between 57.5 and 60.8 GHz, a 15 dB voltage gain, and a 9 dB noise figure. Two-tone measurements show ?12.5 dBm IIP3, 29 dBm IIP2, and ?24 dBm ICP1. The PC-PLL phase noise is ?105 dBc/Hz at 1 MHz offset from a 20 GHz carrier, and the phase of the received 60 GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80 mA from a 1.2 V supply, and measures 1,400 μm × 660 μm (900 μm × 500 μm excluding pads) including LNAs, mixers, and PC-PLL in a 90 nm RF CMOS process.     

X波段低变频损耗混频器设计

采用商用肖特基势垒二极管HSMS-2822,研制了低变频损耗、高隔离度X波段单平衡混频器。为实现所需要的混频带宽,本振信号和射频信号采用三分支定向耦合器耦合输入,仿真研究表明其能有效地改善工作频率带宽,提高本振端口与射频端口间的隔离度。通过设计合理的空闲频率回收电路,回收利用空闲频率能量,能有效地降低混频器变频损耗,提高本振信号、射频信号及空闲频率信号到中频端口的隔离度。在10.6GHz,测得最小变频损耗5.67dB;在10～11.5GHz,混频器变频损耗为6.4±0.7dB,变频损耗平坦度好,RF-IF隔离度优于27dB,LO-IF隔离度高于24dB,LO-RF隔离度优于14dB。