分步电镀法制备Sn-Ag-In三元凸点及其可靠性

本文介绍了一种制备细节距、元素分布均匀的Sn-Ag-In三元凸点的方法。其特征在于在Cu凸点下金属层上分步电镀Sn-Ag和In,通过精确控制回流过程,获得了Sn1.8Ag9.4In凸点。研究发现位于Sn-Ag-In焊料和Cu之间的金属间化合物厚度随回流时间的延长而生长,这使得焊料基体中Ag相对浓度增加,因此在凝固过程中,更多的Ag2In相析出,起到了颗粒增强的作用。     

微尺寸SnAg凸点的制备技术及其互连可靠性

用电镀法制备了尺寸小于100μm的面阵列Sn-3.0Ag凸点.芯片内凸点的高度一致性约1.42%,Φ100mm硅圆片内的高度一致性约3.57%,Ag元素在凸点中分布均匀.研究了不同回流次数下SnAg/Cu的界面反应和孔洞形成机理,及其对凸点连接可靠性的影响.回流过程中SnAg与Cu之间Cu6Sn5相的生长与奥氏熟化过程相似.SnAg/Cu6Sn5界面中孔洞形成的主要原因是相转变过程中发生的体积缩减.凸点的剪切强度随着回流次数的增多而增大,且多次回流后SnAg/Cu界面仍然结合牢固.Cu6Sn5/Cu平直界面中形成的孔洞对凸点的长期可靠性构成威胁.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than ±0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260°C in N₂ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150°C for 1000 h in N₂ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs     

Under bump metallurgy study for Pb-free bumping

The demand for Pb-free and high-density interconnection technology is rapidly growing. The electroplating-bumping method is a good approach to meet finepitch requirements, especially for high-volume production, because to volume change of patterned-solder bumps during reflow is not so large compared with the stencil-printing method. This paper proposes a Sn/3.5 Ag Pb-free electroplating-bumping process for high-density Pb-free interconnects. It was found that a plated Sn/Ag bump becomes Sn/Ag/Cu by reflowing when Cu containing under bump metallurgy (UBM) is used. Another important issue for future flip-chip interconnects is to optimize the UBM system for high-density and Pb-free solder bumps. In this work, four UBM systems, sputtered TiW 0.2 μm/Cu 0.3 μm/electroplated Cu 5 μm, sputtered Cr 0.15 μm/Cr-Cu 0.3 μm/Cu 0.8 μm, sputtered NiV 0.2 μm/Cu 0.8 μm, and sputtered TiW 0.2 μm/NiV 0.8 μm, were investigated for interfacial reaction with electroplated Pb/63Sn and Sn/3.5Ag solder bumps. Both Cu-Sn and Ni-Sn intermetallic compound (IMC) growth were observed to spall-off from the UBM/solder interface when the solder-wettable layer is consumed during a liquid-state “reflow” process. This IMC-spalling mechanism differed depending on the barrier layer material.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70 μm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as ±3 μm between different substrates after reflow process; ±2.5 μm in single substrate; and even ±1 μm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.     

Lead-Free Bumping Using an Alternating Electromagnetic Field

A novel lead-free bumping technique using an alternating electromagnetic field (AEF) was investigated. Lead-free solder bumps reflowed onto copper pads through AEF have been achieved. A comparison was conducted between the microstructures of the lead-free solder joints formed by the conventional thermal reflow and AEF reflow. Keeping the substrate temperature lower than that of the solder bumps, AEF reflow successfully created metallurgical bonding between the lead-free solders and metallizations through an interfacial intermetallic compound (IMC). The AEF reflow could be finished in several seconds, much faster than the conventional hot-air reflow. Considering the morphology of the interfacial Cu₆Sn₅ IMC, a shorter heating time above the melting point would be a better choice for solder joint reliability. The results show that AEF reflow is a promising localized heating soldering technique in electronic packaging.     

Effects of Cu contents in Pb-free solder alloys on interfacial reactions and bump reliability of Pb-free solder bumps on electroless Ni-P under-bump metallurgy

Using the screen-printed solder-bumping technique on the electroless plated Ni-P under-bump metallurgy (UBM) is potentially a good method because of cost effectiveness. As SnAgCu Pb-free solders become popular, demands for understanding of interfacial reactions between electroless Ni-P UBMs and Cu-containing Pb-free solder bumps are increasing. It was found that typical Ni-Sn reactions between the electroless Ni-P UBM and Sn-based solders were substantially changed by adding small amounts of Cu in Sn-based Pb-free solder alloys. In Cu-containing solder bumps, the (Cu,Ni)₆Sn₅ phase formed during initial reflow, followed by (Ni,Cu)₃Sn₄ phase formation during further reflow and aging. The Sn3.5Ag solder bumps showed a much faster electroless Ni-P UBM consumption rate than Cu-containing solder bumps: Sn4.0Ag0.5Cu and Sn0.7Cu. The initial formation of the (Cu,Ni)₆Sn₅ phase in SnAgCu and SnCu solders significantly reduced the consumption of the Ni-P UBM. The more Cu-containing solder showed slower consumption rate of the Ni-P UBM than the less Cu-containing solder below 300°C heat treatments. The growth rate of the (Cu,Ni)₆Sn₅ intermetallic compound (IMC) should be determined by substitution of Ni atoms into the Cu sublattice in the solid (Cu,Ni)₆Sn₅ IMC. The Cu contents in solder alloys only affected the total amount of the (Cu,Ni)₆Sn₅ IMC. More Cu-containing solders were recommended to reduce consumption of the Ni-based UBM. In addition, bump shear strength and failure analysis were performed using bump shear test.     

Effects on Undercooling and Interfacial Reactions with Cu Substrates of Adding Bi and In to Sn-3Ag Solder

This study investigated the effects of adding Bi and In to Sn-3Ag Pb-free solder on undercooling, interfacial reactions with Cu substrates, and the growth kinetics of intermetallic compounds (IMCs). The amount of Sn dominates the undercooling, regardless of the amount or species of further additives. The interfacial IMC that formed in Sn-Ag-Bi-In and Sn-In-Bi solders is Cu₆Sn₅, while that in Sn-Ag-In solders is Cu₆(Sn,In)₅, since Bi enhances the solubility of In in Sn matrices. The activation energy for the growth of IMCs in Sn-Ag-Bi-In is nearly double that in Sn-Ag-In solders, because Bi in the solder promotes Cu dissolution. The bright particles that form inside the Sn-Ag-In bulk solders are the ζ-phase.     

焊料凸点回流时的桥接现象研究

在用回流焊料凸点时,常会发生凸点的桥接现象,致使芯片报废。此时,相邻的多个凸点彼此融合,聚集成一个更大的焊料球,并吸干先前各凸点中的焊料。本文研究了电镀PbSn凸点和蒸发铟凸点的回流过程中出现的桥接现象。介绍了桥接现象产生的过程及其背景,分析了桥接现象的机理,提出了改进措施。     

Manufacturing of Cu/electroless nickel/Sn-Pb flip chip solder bumps

A process for manufacturing Cu/electroless Ni/Sn-Pb solder bump is discussed in this paper. An attempt to replace zincation with a Cu film as an active layer for the electroless Ni (EN) deposition on Al electrode on Si wafer is presented. Cu/electroless Ni is applied as under bump metallurgy (UBM) for solder bump. The Cu film required repeated etches with nitric acid along with activation to achieve a satisfactory EN deposit. Fluxes incorporating rosin and succinic acid were investigated for wetting kinetics and reflow effectiveness of the electroplated solder bump. The solder plating current density and the reflow condition for achieving solder bumps with uniform bump height were described. The Cu/EN/Sn-Pb solder system was found to be successfully produced on Al terminal in this study that avoids using zincating process     

Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads

The microstructure of the flip-chip solder joints fabricated using stud bumps and Pb-free solder was characterized. The Au or Cu stud bumps formed on Al pads on Si die were aligned to corresponding metal pads in the substrate, which was printed with Sn-3.5Ag paste. Joints were fabricated by reflowing the solder paste. In the solder joints fabricated using Au stud bumps, Au-Sn intermetallics spread over the whole joints, and the solder remained randomly island-shaped. The δ-AuSn, ε-AuSn₂, and η-AuSn₄ intermetallic compounds formed sequentially from the Au stud bump. The microstructure of the solder joints did not change significantly even after multiple reflows. The AuSn₄ was the main phase after reflow because of the fast dissolution of Au. In the solder joints fabricated using Cu stud bumps, the scallop-type Cu₆Sn₅ intermetallic was formed only at the Cu interface, and the solder was the main phase. The difference in the microstructure of the solder joints with Au and Cu stud bumps resulted from the dissolution-rate difference of Au and Cu into the solder.     

Void detection in solder bumps with deep learning

Wafer level chip scale packages feature large numbers of solder bumps. These bumps are prone to having voids arising for instance from outgassing during the solder reflow. These voids are considered a reliability risk for the thermo-mechanical strength of the solder connection. Screening of bumps on void percentage is therefore required for quality control. Voids are well captured with X-ray radiography. Void detection in X-ray images is the topic of this paper. The large number of solder bumps necessitates the detection to be automated. In this article we first employ conventional threshold based methods to identify voids. Then, we apply a deep learning model to void percentage detection. We will demonstrate that with a proper training data set deep learning can successfully bin solder bumps on their void percentage.     

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Characterization of small-sized eutectic Sn-Bi solder bumps fabricated using electroplating

We studied the effects of the cooling rate during the reflow process on the microstructure of eutectic Sn-Bi solder bumps of various sizes fabricated by electroplating. To fabricate eutectic Sn-Bi solder bumps of less than 50 μm in diameter, Sn-Bi alloys were electroplated on Cu pads and reflowed at various cooling rates using the rapid thermal annealing system. The interior microstructure of electroplated bumps showed a fine mixture of Sn-rich phases and Bi-rich phases regardless of the cooling rate. Such an interior microstructure of electroplated bumps was quite different from the reported microstructure of vacuum-evaporated bumps. Ball shear tests were performed to study the effects of the cooling rate on the shear strength of the solder bumps and showed that the shear strength of the bumps increased with increasing cooling rate probably due to the reduced grain size. Soft fractures inside the solder bump were observed during the ball shear test regardless of the cooling rate.     

Interfacial reaction between multicomponent lead-free solders and Ag,Cu, Ni,and Pd substrates

The interfacial reaction between two prototype multicomponent lead-free solders, Sn-3.4Ag-1Bi-0.7Cu-4In and Sn-3.4Ag-3Bi-0.7Cu-4In (mass%), and Ag, Cu, Ni, and Pd substrates are studied at 250°C and 150°C. The microstructural characterization of the solder bumps is carried out by scanning electron microscopy (SEM) coupled with energy dispersive x-ray analysis. Ambient temperature, isotropic elastic properties (bulk, shear, and Young’s moduli and Poisson’s ratio) of these solders along with eutectic Sn-Ag, Sn-Bi, and Sn-Zn solders are measured. The isotropic elastic moduli of multicomponent solders are very similar to the eutectic Sn-Ag solder. The measured solubility of the base metal in liquid solders at 250°C agrees very well with the solubility limits reported in assessed Sn-X (X=Ag, Cu, Ni, Pd) phase diagrams. The measured contact angles were generally less than 15° on Cu and Pd substrates, while they were between 25° and 30° on Ag and Ni substrates. The observed intermediate phases in Ag/solder couples were Ag₃Sn after reflow at 250°C and Ag₃Sn and ζ (Ag-Sn) after solid-state aging at 150°C. In Cu/solder and Ni/solder couples, the interfacial phases were Cu₆Sn₅ and (Cu,Ni)₆Sn₅, respectively. In Pd/solder couples, only PdSn₄ after 60-sec reflow, while both PdSn₄ and PdSn₃ after 300-sec reflow, were observed.     

Effect of cooling rate on the isothermal fatigue behavior of CBGAsolder joints in shear

This paper investigates the distribution characteristics of the isothermal fatigue lifetime of ceramic ball grid array (CBGA) solder joints in shear. Placement direction of the board-level assembly on the oven conveyor during reflow critically influences the fatigue lifetime of solder joints in shear: the front or outer solder joints have a longer shear lifetime than the rear or inner ones. The solder joints that moved diagonally during reflow have a longer fatigue lifetime and a tighter distribution. Cracks initiated in the eutectic solder region on the card and package side and tend to propagated in that region, while final failure occurred mainly on the card-said eutectic solder region. This phenomenon can be explained that the front or outer solder bumps have a resistant effect to the gas fluid which passes through the rear or inner solder bumps, and lower these solder joints' cooling rate during solidification. Fast cooling rate can cause a more fine-grained and homogeneous microstructure in eutectic solder alloy, which can delay crack initiation and slow crack growth. When the board-level assembly moves diagonally during reflow, the resistant effect of front solder bumps to the gas fluid reduces markedly. So the fatigue lifetime of solder joints and its distribution characteristic enhance substantially. The theories of fluid dynamics and heat transmission are used to calculate the decrease of gas fluid velocity and the corresponding reduction of mean coefficient of heat transfer (h_m)     

Formation of a Metastable Phase at the Interface Between Sn and Ag–Pd Substrates During Liquid-State Reaction

Ag–Pd alloys are widely used as thick-film conductors and are potential alternatives to the expensive Au bump. In this work, because Sn is the primary element in solders, we investigated Sn/Ag–Pd interfacial reactions at 250°C as a means of assessing the reliability and evaluating reflow reactions at joints between solder and Ag–Pd conductor contacts, and in the Ag bump combined with the solder cap. The experimental results showed that Sn/Ag–Pd interfacial reactions at 250°C are different from those of Sn/Ag and Sn/Pd. A metastable Sn–Ag–Pd ternary phase is formed when the amount of Pd added is 20–40 at.%. Because, in commercial applications, at least 20 wt.% Pd (~20 at.% Pd) is used in Ag–Pd alloys to eliminate the silver-migration phenomenon, assessment of the reliability of Ag bumps and the soldered joints of Ag–Pd thick film hybrid circuits must be based on Sn/Ag–Pd interfacial reactions, not those of Sn/Pd and Sn/Ag.