薄层SOS薄膜材料外延生长及其器件应用

亚微米CMOS/SOS器件发展对高质量的100-200纳米厚度的薄层SOS薄膜提出了更高的要求.实验证实;采用CVD方法生长的原生SOS薄膜的晶体质量可以通过固相外延工艺得到明显改进.该工艺包括:硅离子自注入和热退火.X射线双晶衍射和器件电学测量表明:多晶化的SOS薄膜固相外延生长导致硅外延层晶体质量改进和载流子迁移率提高.固相外延改进的薄层SOS薄膜材料能够应用于先进的CMOS电路.     

Co/Si/Ti/Si(100)多层薄膜固相反应异质外延生长CoSi_2薄膜

本文研究Ｓｉ中间淀积层对ＣｏＳｉ２／Ｓｉ（１００）固相异质外延的影响．用离子束溅射方法在Ｓｉ（１００）衬底上制备了Ｃｏ／Ｓｉ／Ｔｉ／Ｓｉ多层薄膜结构，通过快速热退火使多层薄膜发生固相反应．实验表明，利用Ｃｏ／Ｓｉ／Ｔｉ／Ｓｉ固相反应得到的ＣｏＳｉ２薄膜具有良好的外延特性，薄膜也具有良好的电学特性和热稳定性．实验发现在较低温度退火时，生成Ｃｏ２Ｔｉ４Ｏ之类化合物，作为扩散阻挡层有利于ＣｏＳｉ２薄膜的外延．在多层薄膜结构中加入Ｓｉ非晶层，既能减少衬底Ｓｉ消耗量，又能保持ＣｏＳｉ２良好外延特性     

硅基GaN薄膜的外延生长

本文报道采用简便的真空反应法在Ｓｉ（１１１）衬底上生长出了六方结构的ＧａＮ单晶薄膜,并对ＧａＮ薄膜的表面形貌、结晶学性质和光学特性作了研究．ＳＥＭ表明外延层表面光亮平整,无裂纹出现,ＸＲＤ图谱上有一ＧａＮ（０００２）衍射峰,其半高宽为０．５°,室温下的光致发光谱在３７３ｎｍ处有一个很强的发光峰,其半高宽为８ｎｍ（３５．７ｍｅＶ）．     

Co／Ti／Si三元固相反应外延生长CoSi2薄膜

研究采用Ｃｏ／Ｔｉ／Ｓｉ三元固相反应的方法生长外延ＣｏＳｉ２薄膜。通过选择适当的热处理条件，采用步退火，在Ｓｉ（１００）和Ｓｉ（１１１）衬底上均成功获得外延ＣｏＳｉ２薄膜。实验用ＸＲＤ．ＴＥＭ、ＲＢＳ／ｃｈａｎｎｅｌｉｎｇ等测试技术分析ＣｏＳｉ２薄膜外延特性，得到的ＣｏＳｉ２／Ｓｉ薄膜的ＲＢＳ／ｃｈａｎｎｅｌｉｎｇ最低产额Ｘｍｉｎ达到１０－１４％，实验时ＣｏＳｉ２／Ｓｉ（１１１）样品，分别沿Ｓｉ衬     

热壁外延生长GaAs／Si薄膜质量研究

本文研究了用热壁外延（HWE）技术在Si衬底上不同工艺下生长的GaAs薄膜的拉曼（Raman)和荧光（PL）光谱。研究表明：在室温下,GaAs晶膜的Raman光谱的265cm^-1横声子（TO）峰和289cm^-1纵声子（LO）峰的峰值之比随晶膜质量的变化而逐渐变大、半高宽（FWHM）变窄且峰值频移动变小,而LC光谱出现在871nm光谱的FWHM较窄,表明所测得的薄膜为单晶晶膜,对同一晶膜也可判断出均匀程度。因此可以通过拉曼光谱和PLC光谱相结合评定外延膜晶体质量。     

750℃下用低压化学汽相沉积在Si上外延生长单晶SiC薄膜

在（１００）硅单晶衬底上，７５０℃外延生长了立方晶系晶向的ＳｉＣ薄膜，该生长温度是目前所报道的最低生长温度。采用一种简单的硅碳比为１：１的甲基硅烷源材料和Ｈ２，，用低压化学汽相沉积工艺生长了ＳｉＣ薄膜。     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

用于先进CMOS电路的150mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

改性的薄SOS膜CMOS器件辐射加固特性

利用注硅固相外延的方法对0.2μm SOS薄硅膜材料进行改性,并制作了单管pMOSFET,nMOSFET及54HC04电路．测量了单管的迁移率,并对样品进行了瞬态辐射实验和总剂量辐射实验,发现用改性后的SOS薄硅膜材料制作的电路,不仅具有同标准0.5μm SOS材料制作的电路相当的动态特性,而且具有很好的抗瞬态辐射能力,并且其抗总剂量辐射能力也达到了很高的水平．     

8英寸薄层硅外延片的均匀性控制方法

8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一.研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3％的前提下,外延层厚度和电阻率形成中间低、边缘略高的“碗状”分布可有效提高晶圆的良率水平.通过调整生长温度和氢气体积流量可实现外延层厚度的“碗状”分布,但调整温区幅度不得超过滑移线的温度门槛值.通过提高边缘温度来提高边缘10 mm和6 mm的电阻率,同时提高生长速率以提高边缘3 mm的电阻率,获得外延层电阻率的“碗状”分布,8英寸薄层硅外延片的的边缘离散现象得到明显改善,产品良率也有由原来的94％提升至98.5％,进一步提升了8英寸薄层硅外延片产业化良率水平.     

Growth Front Evolution of GaN Thin Films on Sapphire Substrate During HVPE

The growth front evolution of GaN thin films deposited on sapphire substrate by hydride vapor phase epitaxity has been studied with atomic force microscope. The evolution of the surface morphology presents four features of stage with the growth process. In initial growth stage, the surface is granular, and the typical grain diameter is about 250nm for t =0.1min. 3D growth plays a key role before the films come up to full coalescence, which causes a rough surface. After 0.1min the growth dimension decreases with the increase of lateral over growth, the surface roughness obviously decreases. From 0.4min to 3min, the growth front roughness increases gradually, and the evolution of the surface roughness exhibits the characteristics of self-affined fractal. Beyond 3min, the root-mean-square decreases gradually, which means the deposition behavior from hyper-2D growth gradually turns into layer growth mode with the increase of growth time.     

Thin Film Silicon Photovoltaic Cells on Paper for Flexible Indoor Applications

The present development of non‐wafer‐based photovoltaics (PV) allows supporting thin film solar cells on a wide variety of low‐cost recyclable and flexible substrates such as paper, thereby extending PV to a broad range of consumer‐oriented disposable applications where autonomous energy harvesting is a bottleneck issue. However, their fibrous structure makes it challenging to fabricate good‐performing inorganic PV devices on such substrates. The advances presented here demonstrate the viability of fabricating thin film silicon PV cells on paper coated with a hydrophilic mesoporous layer. Such layer can not only withstand the cells production temperature (150 °C), but also provide adequate paper sealing and surface finishing for the cell's layers deposition. The substances released from the paper substrate are continuously monitored during the cell deposition by mass spectrometry, which allows adapting the procedures to mitigate any contamination from the substrate. In this way, a proof‐of‐concept solar cell with 3.4% cell efficiency (41% fill factor, 0.82 V open‐circuit voltage and 10.2 mA cm^?2 short‐circuit current density) is attained, opening the door to the use of paper as a reliable substrate to fabricate inorganic PV cells for a plethora of indoor applications with tremendous impact in multi‐sectorial fields such as food, pharmacy and security.     

MOCVD Growth of Device—quality GaN on Sapphire

An AIN Layer grown by an ALE has been developed to improve the growth quality of GaN ON Al2O3 substrate by low-pressure metalorganic vapor phase epitaxy(LP-MOVPE).An ALE AIN layer grown on Al2O3 substrate has a high quality and the structure is similar to GaN, this AIN layer can release the stress between Al2O3 substrate and GaN epilayer.By using this method, the orientation of substrate is extended to GaN epilayer, and the column tilt and the twist are improved, so as to obtain the device-quality GaN.     

用于制备SOI材料的基于硅片键合和双层多孔硅剥离的薄外延硅膜转移技术

采用在阳极化反应时改变电流强度的办法 ,在高掺杂的 P型硅 (111)衬底上制备了具有不同多孔度的双层结构多孔硅层 .用超高真空电子束蒸发技术在多孔硅表面外延生长了一层高质量的单晶硅膜 .在室温下 ,该外延硅片同另一生长有热二氧化硅的硅片键合在一起 ,在随后的热处理过程中 ,键合对可在多孔硅处裂开 ,从而使外延的单晶硅膜转移到具有二氧化硅的衬底上以形成 SOI结构 .扫描电镜、剖面投射电镜、扩展电阻和霍尔测试表明 SOI样品具有较好的结构和电学性能     

氢原子在Cat-CVD法制备多晶硅薄膜中的作用

采用钨丝催化化学气相沉积(Cat—CVD)方法制备多晶硅(p-Si)薄膜,研究氢气稀释率(FR(H2)／(FR(H2) FR(SiH4))对制备多晶硅薄膜的影响。XRD和喇曼光谱分析分别显示(111)面取向的多晶硅峰及喇曼频移为520cm^-1多晶硅峰的强度随氢气稀释率的增加而增强,由喇曼光谱计算的结晶度也有同样的趋势。通过分析测试结果得出,氢原子以表面脱氢、刻蚀弱的Si—Si键．及进入晶格内部进行深度脱氢等方式改善薄膜材料的结晶度。