Silicon p-n junction photodiodes sensitive to ultraviolet radiation

Experimental studies on a silicon photodiode have been carried out to achieve the performance characteristics required for applications such as spectroscopic measurements. Sheet resistance was applied as a control parameter for diffusion to obtain a shallow junction less than 1 µm in depth. For high ultraviolet responsivity, the diffusion layer, in which a built-in field is induced by the impurity gradient, was optimized for values of the sheet resistance of about 800-2000 Ω/□. The device responded in the wavelength range of 200-1000 nm,and had a responsivity of 0.065 A/W at 200 nm. In order to reduce influence of stray light in spectroscopic measurements, two types of photodiodes were fabricated with photoresponse reduced in the long-wavelength portion. A p⁺-n-p⁺device was found preferable to a p⁺-n-n⁺device. And the device structure with an extended electrode was desirable for high, reliable performance.     

Experimental characterization of gold-doped infrared-sensing MOSFET's

The operation of a new type of infrared photon detector is described. This device is a gold-doped n-channel MOSFET that employs impurity photoionization to modulate its drain-to-source conductance. A simple mathematical model is developed whereby the infrared-sensing MOSFET (IRFET) can be analyzed, and experimental results that verify the model are provided. The near-infrared, i.e., wavelengths from 1.38 to 3.54 µm, response of gold impurity centers in the space-charge region behind the strong surface inversion layer of a MOSFET is shown to correspond to the characteristics observed previously by other authors for the gold centers in bulk silicon. A static read-only memory capability and high responsivity, typically 4 mW/µJ, are the most significant IRFET characteristics. Applications in large-scale-integrated imaging arrays are anticipated.     

A batch-fabricated silicon thermopile infrared detector

A thermopile infrared detector fabricated using silicon integrated-circuit technology is described. The device uses a series-connected array of thermocouples whose hot junctions are supported an a thin silicon membrane formed using anisotropic etching and a diffused boron etch stop. The membrane size and thickness control the speed and responsivity of the structure, which can be designed for a given application. For a 2-mm × 2-mm × 1-µm silicon membrane containing sixty bismuth-antimony couples, the structure produces a responsivity of 6 V/W and a time constant of about 15 ms. The use of polysilicon-gold couples can improve the responsivity to nearly 10 V/W while maintaining the same speed, simplifying the process, and retaining compatibility with on-chip signal processing circuitry.     

Selective epitaxial growth for the fabrication of CMOS integrated circuits

A process is described for the fabrication of CMOS integrated circuits which combines the epitaxial lateral overgrowth (ELO) technique with the concept of selective epitaxy. The resulting epitaxial material is shown to have a low defect density. Transistors fabricated in the selective epitaxy are shown to have characteristics which are a function of the epitaxial deposition conditions, the substrate orientation and dopant concentration, and the epitaxial layer thickness. Minimum device leakage currents were 250 pA/µm of channel width for n-channel devices fabricated in a p-well and 1.0 pA/µm for devices fabricated on p-substrates. The higher leakage currents for devices fabricated in a well are believed to be a result of the narrow vertical spacing (0.3-0.5 µm) between the n⁺source-drain regions and the n⁺substrate.     

Silicon-on-insulator bipolar transistors

Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.     

Ion-implanted FET for power applications

High-energy ion implantation is coupled with the conventional planar technology to realize a silicon FET for power application. This device known as "Gridistor" is a multichannel FET with a p-type buried as gate. Boron implantation at various energies (600-900 keV) through a metallic mask are used to do a high-doped p-type gate layer, 0.8 µ thick and buried 1 µ below the surface. Since there is no implantation induced defects in the active regions of the device, low annealing temperature can be effectively used. As a consequence, the pattern sharpness is only limited by the definition of the mask. Using ion-etched gold layer as mask, 1 µ wide channels are made in a reproductible way. Few test structures have been made to check the behavior of implantation and planar technologies by measuring their capaci tances, transconductance, and I-V characteristics.     

Fabrication of MSM photoconductor on porous Si using micromachined silicon mask

An MSM photoconductive detector has been fabricated from porous silicon using a micromachined silicon mask instead of photolithography. This approach allows damage to porous silicon that can be caused by chemical processing to be avoided. The interdigitated pattern of the silicon mask with a finger spacing of approximately 150 mu m and finger width of 50 mu m was made using silicon micromachining. The fabricated MSM porous silicon photoconductive detector, which exhibits responsivities of better than 0.5 A/W at the wavelength of the He-Ne laser (6280 AA) and a dark current of 950 nA at 10 V, is very promising as an optoelectronic device.<>     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

InP MISFET's with plasma anodic Al2O3and interlayed native Oxide gate insulators

InP MISFET's, with native oxide film interlayed between plasma anodic Al2O3film and the InP substrate, has been fabricated and showed the instability of the drain current reduced less than ± 4 percent for the period of 5 µs ∼ 5 × 10⁴s. The effective electron mobility is 2100 ∼ 2600 cm²/V.s at room temperature. The CV characteristics of MIS diodes and AES in-depth profiles are also discussed with respect to effects of interlaying native oxide film on device characteristics.     

A low-voltage high-speed silicon photodiode with buried isolation region for short-haul optical-fiber communications

A new epitaxial silicon p-i-n photodiode has been developed for short-haul optical-fiber communications that can be operated at biases as low as 4 V. The device has a heavily doped 5-µm-thick p⁺⁺isolation-region between the p⁺substrate and the π-epitaxial layer. Fast rise and fall times (2 ns), and low leakage current (40 pA) result from the recombination and trapping of the minority-carrier electrons in the substrate. Experimental results on such an n⁺-π-p⁺⁺-p⁺device with 1.1-mm²photosensitive area and 25-µm epi-layer thickness show quantum efficiency of 80 percent at 825-nm wavelength.     

A novel heterostructure interdigital photodetector (HIP) with picosecond optical response

The demonstration of a novel and simple heterostructure interdigital photodetector (HIP) is reported. The detector displays 50- 60 ps symmetric rise and fall times, low operating voltages (∼10-25V), with a dc responsivity greater than 0.3 A/W at λ = 0.83 µm. The results obtained are comparable to the fastest commercial high speed detectors available today. The device is compatible with planar technology and thus should lend itself to integration with MESFET's or other microwave integrated circuits. Lastly, the concept of using a heterostructure to confine the injected carriers should ultimately provide high speed operation by limiting the detrimental effects of carrier diffusion and traps in the semi-insulating substrate.     

Study and fabrication of PIN photodiode by using ZnSe/PS/Sistructure

In this experiment, the PIN photodiode by using ZnSe/porous Si/Si structure was investigated. The single crystal ZnSe epilayer is successfully grown on porous silicon substrate with CVD system. Indium is as a dopant to reduce the resistivity of ZnSe intrinsic layer. To control the different thickness of n-ZnSe layer will change the photocurrent and responsivity of the ZnSe PIN diode. The best diffusion conditions are diffusion temperature of 300°C and driving time of 30 min. The responsivity of device is 0.03 A/W. In addition, the dark current of the photodiode is near zero     

InGaPAs-InP double-heterojunction high-radiance LED's

InGaPAs-InP double-heterojunction (DH) high-radiance LED's (λ ∼ 1.05-1.3 µm) have been fabricated by liquid-phase epitaxy (LPE) at constant temperature. The crystal growth procedure is described and the influence of InP substrate crystalline perfection is discussed. LED's with a high-radiance geometry suitable for coupling to an optical fiber have been fabricated. The four-layer double-heterostructure LED's have low forward-biased resistances. Typical external quantum efficiencies of ∼1.5 percent and narrow emission linewidths (∼56 nm, typical), have been measured for LED's (λ ∼ 1.08 µm) with an InGaPAs active layer thickness of 1.6 µm and an active layer carrier concentration ofN_{A} - N_{D} approx 2.8 \× 10^{16}cm^-3. The dependence of LED emission linewidth upon active layer doping is reported. Transient measurements show that the LED rise time is dependent upon current density for high-injection conditions. Preliminary lifetest results demonstrate only slight LED degradation after operation at 50 and 70°C for times up to ∼3500 h.     

Structure and properties of silicon carbide grown on porous substrate by vacuum sublimation epitaxy

A SiC layer was grown by vacuum sublimation epitaxy on porous silicon carbide. A porous SiC layer about 10 μm thick was fabricated by electrochemical etching of an off-axis 6H-SiC substrate. The epitaxial layer was ∼ 10 μm thick. Structural and optical properties of the initial substrate and the porous and epitaxial layers were investigated by X-ray, IR-reflection and photoluminescence methods. An epitaxial SiC layer grown on porous SiC exhibits improved characteristics when compared to a SiC layer on a conventional substrate. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 36, No. 7, 2002, pp. 812–816. Original Russian Text Copyright ? 2002 by Savkina, Ratnikov, Rogachev, Shuman, Tregubova, Volkova.     

Amorphous silicon/silicon carbide heterojunction bulk unipolar diodes (HEBUD)

A new hydrogenated amorphous silicon/silicon carbide heterojunction bulk unipolar diode (HEBUD) has been successfully fabricated. The sawtooth-shaped composition wave of α-SiC:H between layers of n-type α-Si:H was made on an ITO/glass substrate by the RF glow-discharge deposition method. Rectification produced by an asymmetric potential barrier is demonstrated. Preliminary results showed that the design principle is feasible, and that the device is stable. The capacitance was constant regardless of bias. A switching time of 15 µs and a propagation delay time of 9 µs were obtained.     

WDM receiver chip with high responsivity

A semiconductor optical amplifier, a grating demultiplexer and a photodiode array were integrated in InGaAsP/InP to form a WDM receiver chip. 10 wavelength channels (TE or TM polarisation) in the 1.54 μm wavelength region with a channel spacing of 2 nm were detected with a crosstalk of less than -20 dB and a responsivity of up to 8 A/W     

Si纳米线阵列波导光栅制备

采用绝缘层上Si(SOI)材料设计制备了3×5纳米线阵列波导光栅(AWG),器件大小为110μm×100μm。利用简单传输法模拟了器件的传输谱,并采用二维时域有限差分(FDTD)模拟中心通道输出光场的稳态分布,模拟结果表明,器件的通道间隔为11 nm,通道间的串扰为18 dB。通过电子束曝光(EBL)和感应耦合等离子(ICP)刻蚀制备了所设计的器件,光输出谱测试分析表明,器件中心通道的片上损耗为9 dB,通道间隔为8.36～10.40 nm,中心输出通道的串扰为6 dB。在误差允许范围内,设计和测试的结果一致。     

Arrayed waveguide grating of 70/spl times/60 /spl mu/m/sup 2/ size based on Si photonic wire waveguides

A miniature arrayed waveguide grating of 70/spl times/60 /spl mu/m/sup 2/ size consisting of Si photonic wire waveguides was designed using complete modelling in the finite-difference time-domain simulation. The device was fabricated onto a silicon-on-insulator substrate and evaluated in the wavelength range around 1.55 /spl mu/m. The clear demultiplexing characteristics were observed with a channel spacing of 11 nm and a loss of less than 1 dB.     

Planar InP/InGaAsP three-dimensional graded-junction avalanche photodiode

A new planar InP/InGaAsP avalanche photodiode, which is fabricated by Be⁺implantation through a dish-shaped InGaAs mask, has been developed. A three-dimensional graded junction is obtained and a uniform gain as high as 30 achieved without edge or surface breakdown. The dish-shaped InGaAs implantation mask is formed by a photoelectrochemical etching technique. Device modeling indicates that the graded junction and low doping concentration can prevent edge breakdown and greatly suppress the surface field. The diode has a separated absorption and multiplication structure grown by hydride vapor-phase epitaxy. These devices exhibit low primary dark currents (≈ 1 nA), and high quantum efficiencies close to that of an InGaAs p-i-n at 1.3-µm wavelength. Sensitivity measurements at bit rates of 1.7 Gbit/s give a minimum average receiver power required for 10^-9BER of -35.5 dBm.     

一种改进的CMOS紫外/蓝光光电二极管的二维响应度物理模型

A CMOS UV and blue-extended photodiode is presented and fabricated for light detection in the ultraviolet/blue spectral range. An octagon homocentric ring-shaped geometry is used to improve the ultraviolet responsivity and suppress edge breakdown. This paper has established a two-dimensional responsivity physical model for the presented photodiode and given some numerical analyses. The dead layer effect, which is caused by the high-doping effects and boron redistribution, is considered when analyzing the distribution of the current of the proposed UV and blue-extended photodiode. In the dead layer, the boron doping profile decreases towards the surface. Simulated results illustrate that the responsivity in the UV range is obviously decreased by the effect of the dead layer, while it is not affected in the visible and near-infrared part of the spectrum. The presented photodiode is fabricated and the silicon tested results are given, which agree well with the simulated ones.