Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator

This paper reports the design and measurement results of a write pulse generator IC for rewritable CD and DVD disk drives implemented in a standard digital 0.35 /spl mu/m CMOS technology. The chip is the interface between a processor and a laser driver. It provides accurate timing signals to the laser driver via a four-level differential current interface. Transitions between current levels are programmable with 149 ps resolution at a data rate of 420 Mb/s, corresponding to 16x DVD write speed. The chip includes a digital core managing the different write strategies, a CMOS serial interface to the processor for programming, a low power, low phase noise, 64-phase ring voltage-controlled oscillator (VCO) based on CMOS inverters, a phase-locked loop (PLL) locking the VCO to the system clock, and a current interface to the laser driver. The PLL phase noise is -144 dBc/Hz at 10 MHz offset from the 105 MHz carrier. At this frequency, the rms jitter is 1.1 ps with 0.8 mA VCO core supply current. The chip is fully ESD protected.     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process     

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clockgeneration

This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100     

A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessorapplications

A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of ±25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310×280 μm² in a 0.25-μm CMOS process, the PLL dissipates 25 mW from a 1.9-V supply     

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.     

A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification

This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5 GHz) 1–3 GHz tunable ring-oscillator PLL for integrated clock multiplier applications. A new loop filter structure based on a sample-reset phase-to-voltage converter and a Gm-C filter decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. The ring-oscillator VCO features programmability of phase noise and power consumption at a given frequency. The PLL is implemented in a digital 0.13 $mu{hbox{m}}$ CMOS process using only 1.2 V devices, occupies 0.07 ${hbox{mm}}^{2}$ and consumes 23 mW excluding reference clock receiver for 2.5 GHz output at the lowest phase noise mode.      

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-mum CMOS process, the PLL occupies 0.15 mm² die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms     

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²     

2-GHz CMOS锁相环时钟发生器研究与设计

采用包含预充电通路,自适应偏置的压控振荡器,设计了一种2-GHz锁相环时钟发生器,并用0.18μm混合信号CMOS工艺实现.分析了环路参数对锁相环输出噪声影响,并对环路参数进行优化.1.8V电源电压下2GHz时钟的rms抖动,peak-peak抖动的测试结果分别为7.27ps,37.5ps,功耗为42mW.     

A PLL clock generator with 5 to 10 MHz of lock range formicroprocessors

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8-μm CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency     

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/sone-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter ζω_n (ζ is a damping factor and ω_n is the natural angular frequency of the PLL), and that the optimization focusing on the ω_n dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-μm Si bipolar technology (f_T = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers)     

A CMOS self-calibrating frequency synthesizer

A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K_o large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K _o to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-μm 3-V digital CMOS process     

1.2V低功耗时钟发生器设计

基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。     

A 1.8~3.2-GHz fully differential GaAs MESFET PLL

A 1.8~3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74~3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8~3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz     

Low-jitter 10 GHz multiphase PLL in 90 nm CMOS

A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively.     

Design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz

This paper is concerned with the design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz. The focus is on the circuit configuration and performance parameters of the basic analog units of the PLL: the stabilized bias unit, phase-frequency detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements on ICs fabricated by a 0.25-or 0.18-μm established CMOS technology. The circuit configurations are presented of VCOs that are tunable up to 1–1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-or 0.18-μm technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consumption, and jitter performance are presented and investigated.     

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.     

低抖动时钟锁相环设计

采用SMIC0.13μm CMOS工艺,设计实现了一个基于自偏置技术的低抖动时钟锁相环。锁相环核心功耗约为8.4～16.8mW,可稳定输出的频率范围为25MHz～2.4GHz,测试结果显示,锁相环锁定在1.36GHz时输出时钟的均方抖动为2.82ps,周期峰峰值抖动为21.34ps。     

A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-μm DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz     

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixedsignal SoCs with a wide range of operating frequencies.The design proposes a multi-regulator PLL architecture,in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator,reducing the parasitic noise and spur coupling between different PLL building blocks.Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-f_(vco)/1%-V_(DD).The design...