Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

Fabrication of Integrated Vertical Mirror Surfaces and Transparent Window for Packaging MEMS Devices

A scheme for creating metal-coated vertical mirrors in silicon, along with an integrated transparent package lid for assembling, packaging, and testing microelectromechanical systems (MEMS) devices is presented. Deep reaction ion etching (DRIE) method described here reduces the loading effect and maintains a uniform etch rate resulting in highly vertical structures. A novel self-masking lithography and liftoff process was developed to ensure that the vertical mirrors undergo uniform metallization while leaving a transparent window for optical probing. Front side of a Si wafer was shallow-etched using DRIE to define an eventual optical window. This surface was then anodically bonded to a Pyrex wafer. Backside Si was then patterned to define thin channels around the optical window. These channels were vertically etched using DRIE, after which the unattached portions of the window region were removed. Negative photoresist was spun on the remaining vertical structures and the stack was exposed from the Pyrex side using Si structures as a self-mask. Subsequent metal sputtering and liftoff results in the metallized top and mirror sidewalls while leaving a clear window. These integrated mirrors and lids are then bonded to the active MEMS mirrors. Various processes and results are illustrated with an example of packaged corner cube retroreflectors (CCRs)     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

DRIE based technology for 3D silicon barcodes fabrication

Microworld barcoding has become a promising tool for cell biology. Individual and subpopulation cell tracking is of great interest to evaluate cell behaviour. Nowadays, many micrometer and even nanometer size silicon structures can be fabricated using microelectronics techniques. In this work we report for first time the development of 3D barcodes based on silicon substrate. The proposed silicon micromachining technology based on deep reactive ion etching (DRIE) allows to obtain micrometer-sized cylindrical structures with vertical etch profile that defines a bit = 1 and non-vertical etch profile that defines a bit = 0. Although this technology will allow more than 15 bits representation, only 4-8 bits are necessary for cell labelling. The results of this work show that DRIE has become a versatile technique to produce high aspect 3D biocompatible silicon-based barcodes structures for cell studies.     

Fabrication and characterization of truly 3-D diffuser/nozzlemicrostructures in silicon

We present microfabrication and characterization of truly three-dimensional (3-D) diffuser/nozzle structures in silicon. Chemical vapor deposition (CVD), reactive ion etching (RIE), and laser-assisted etching are used to etch flow chambers and diffuser/nozzle elements. The flow behavior of the fabricated elements and the dependence of diffuser/nozzle efficiency on structure geometry has been investigated. The large freedom of 3-D micromachining combined with rapid prototyping allows one to characterize and optimize diffuser/nozzle structures     

A pendulous oscillating gyroscopic accelerometer fabricated using deep-reactive ion etching

A silicon pendulous oscillating gyroscopic accelerometer (POGA) was fabricated using deep-reactive ion etching (DRIE) and silicon wafer bonding technologies. A POGA is the micromachining-compatible analog of the pendulous integrating gyroscopic accelerometer (PIGA), which is the basis of the most sensitive accelerometers demonstrated to date. Gyroscopic accelerometers rely on the principle of rebalancing an acceleration-sensing pendulous mass by means of an induced gyroscopic torque. The accelerometer is composed of three individual layers that are assembled into the final instrument. The top layer uses wafer bonding of an oxidized wafer to a handling wafer to create a silicon-on-oxide wafer pair, in which the oxide layer provides electrical isolation between the mechanical members and the handling layer. The middle layer is a two-gimbal torsionally-supported silicon structure and is in turn supported by an underlying drive/sense layer. The micromachined POGA operated according to gyroscopic accelerometer principles, having better than milligram resolution and dynamic ranges in excess of 1 g (open loop) and approximately 12 mg (closed loop).     

Effect of process parameters on the surface morphology andmechanical performance of silicon structures after deep reactive ionetching (DRIE)

The ability to predict and control the influence of process parameters during silicon etching is vital for the success of most MEMS devices. In the case of deep reactive ion etching (DRIE) of silicon substrates, experimental results indicate that etch performance as well as surface morphology and post-etch mechanical behavior have a strong dependence on processing parameters. In order to understand the influence of these parameters, a set of experiments was designed and performed to fully characterize the sensitivity of surface morphology and mechanical behavior of silicon samples produced with different DRIE operating conditions. The designed experiment involved a matrix of 55 silicon wafers with radius hub flexure (RHF) specimens which were etched 10 min under varying DRIE processing conditions. Data collected by interferometry, atomic force microscopy (AFM), profilometry, and scanning electron microscopy (SEM), was used to determine the response of etching performance to operating conditions. The data collected for fracture strength was analyzed and modeled by finite element computation. The data was then fitted to response surfaces to model the dependence of response variables on dry processing conditions     

Process Development for CMOS-MEMS Sensors With Robust Electrically Isolated Bulk Silicon Microstructures

This paper presents a deep reactive-ion etching (DRIE)-based post-CMOS micromachining process that provides robust electrically isolated single-crystal silicon (SCS) microstructures for integrated inertial sensors. Several process issues arise from previously reported three-axis CMOS microelectromechanical system (MEMS) accelerometers, including sidewall contaminations of SCS microstructures in plasma etch and a severe silicon undercut caused by overheating of suspended microstructures. Solutions to these issues have been found and are discussed in detail in this paper. In particular, a lumped-element model is developed to estimate the temperature rise on suspended microstructures in a silicon DRIE process. Based on the thermal modeling and experiments, a thick photoresist layer has been used as a thermal path to avoid the severe silicon undercut. The sidewall contamination problem is also eliminated using the modified CMOS-MEMS process. A three-axis accelerometer with a low-noise, low-power on-chip amplifier has been successfully fabricated using the new process. Footing effect was observed on the backside of the sensor microstructure, but it has little effect on the structural integrity and sensitivity of the sensor.     

Front-to-backside alignment using resist-patterned etch control andone etching step

A processing technique that aligns features on the front side of a wafer to those on its backside has been developed for bulk micromachining. A 30 μm-square and 1.6 μm-thick diaphragm serves as an alignment pattern. At the same time that the alignment diaphragm is made, much thicker, large-area diaphragms can be partially etched using `mesh' masking patterns in these areas. The mesh-masking technique exploits the etch-rate differences between (100) and (111) planes to control the depths reached by etch pits in selected areas. The large partially etched diaphragms (2 to 3 mm², roughly 100 μm thick) are sufficiently robust to survive subsequent IC-processing steps in a silicon-foundry environment. The thin alignment diaphragm can be processed through these steps because of its very small area. The partially etched diaphragms can be reduced to useful thicknesses in a final etch step after the circuits have been fabricated     

Etch-induced stress failures of SiO2 cantilever beams

Acute angles formed in the underlying silicon during anisotropic etching to free silicon dioxide cantilever beams are found to be the point of maximum stress during etch. Consequently, failures of the cantilever structure originate at these locations. The origin of this stress concentration is due to mechanical loading of the cantilever during etch, and this loading effect is smaller for shorter or narrower cantilevers. Finite element modelling of a partially etched cantilever microstructure, as used to predict the location of maximum stress, as well as the probable vector direction failures, will follow. Cantilevers free of etch-induced failure are fabricated by isotropic etching and by the modification of etch geometry through the addition of ribbed segments to the cantilever.     

Post-CMOS processing for high-aspect-ratio integrated siliconmicrostructures

Presents a new fabrication sequence for integrated-silicon microstructures designed and manufactured in a conventional complementary metal-oxide-semiconductor (CMOS) process. The sequence employs a post-CMOS deep silicon backside etch, which allows fabrication of high aspect ratio (25:1) and flat (greater than 10 mm radius of curvature) MEMS devices with integrated circuitry. A comb-drive resonator, a cantilever beam array and a z-axis accelerometer were fabricated using this process sequence. Electrical isolation of single-crystal silicon was realized by using the undercut of the reactive ion etch (RIE) process. Measured out-of-plane curling across a 120-μm-wide 25-μm-thick silicon released plate was 0.15 μm, which is about ten times smaller than curl of the identical design as a thin-film CMOS microstructure. The z-axis DRIE accelerometer structure is 0.4 mm by 0.5 mm in size and has a 25-μm-thick single-crystal silicon proof mass. The measured noise floor is 1 mG/√Hz, limited by electronic noise. A vertical electrostatic spring "hardening" effect was theoretically predicted and experimentally verified     

Integration of Trench-Isolated Through-Wafer Interconnects with 2D Capacitive Micromachined Ultrasonic Transducer Arrays

This paper presents a method to provide electrical connection to a 2D capacitive micromachined ultrasonic transducer (CMUT) array. The interconnects are processed after the CMUTs are fabricated on the front side of a silicon wafer. Connections to array elements are made from the back side of the substrate via highly conductive silicon pillars that result from a deep reactive ion etching (DRIE) process. Flip-chip bonding is used to integrate the CMUT array with an integrated circuit (IC) that comprises the front-end circuits for the transducer and provides mechanical support for the trench-isolated array elements. Design, fabrication process and characterization results are presented. The advantages when compared to other through-wafer interconnect techniques are discussed.     

The surface/bulk micromachining (SBM) process: a new method forfabricating released MEMS in single crystal silicon

This paper presents the surface/bulk micromachining (SBM) process to allow fabricating released microelectromechanical systems using bulk silicon. The process starts with a (111)-oriented silicon wafer. The structural patterns are defined using the reactive ion etching technique used in surface micromachining. Then the patterns, as well as sidewalls, are passivated with an oxide film, and bare silicon is exposed at desired areas. The exposed bare silicon is further reactive ion etched, which defines sacrificial gap dimensions. The final release is accomplished by undercutting the exposed bulk silicon sidewalls in aqueous alkaline etchants. Because {111} planes are used as etch stops, very clean structural surfaces can be obtained. Using the SBM process, 5-, 10-, and 100-μm-thick arbitrarily-shaped single crystal silicon structures, including comb-drive resonators, at 5-, 30-, and 100-μm sacrificial gaps, respectively, are fabricated. An electrostatic actuation method using p-n junction isolation is also developed in this paper, and it is applied to actuate comb-drive resonators. The leakage current and junction capacitance of the reversed-biased p-n junction diodes are also found to be sufficiently small for sensor applications. The developed SBM process is a plausible alternative to the existing micromachining methods in fabricating microsensors and microactuators, with the advantage of using single crystal silicon     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

Miniaturization of Electrostatic Fluid Accelerators

Existing thermal-management methods for electronics do not meet the technology needs and remain a major bottleneck in the evolution of computing, sensing, and information technology. The decreasing size of microelectronic components and the resulting increasing thermal output density require novel cooling solutions. Electrostatic fluid accelerators (EFAs), also known as electrohydrodynamic ionic wind pumps, have the potential of becoming a critical element of electronic thermal-management solutions. In order to take full advantage of EFA-based thermal management, it is essential to miniaturize EFA technology. This paper demonstrates the successful operation of a mesoscale microfabricated silicon EFA. Several cantilever structures fabricated in bulk silicon with radii of tip curvature ranging from 0.5 to 25 mum are used as the corona electrode. The device was fabricated using the combination of deep reactive ion etching (DRIE) and reactive ion etch (RIE) microfabrication processes. Forced convection cooling is demonstrated using infrared imaging, showing a 25degC surface temperature reduction over an actively heated substrate. The fabrication and test results of a mesoscale microfabricated EFA are presented in this paper.     

一种圆片级硅三层键合的三明治加速度传感器

提出了一种利用体微机械加工技术制作的硅三层键合电容式加速度传感器.采用硅各向异性腐蚀和深反应离子刻蚀技术实现中间梁一质量块结构的制作,通过玻璃软化键合方法完成上、下电极的键合.在完成整体结构圆片级真空封装的同时通过引线腔结构方便地实现了中间电极的引线.传感器芯片大小为6.8 mm×5.6 mm×l.26 ITUTI,其中敏感质量块尺寸为3.2 mm×3.2 mm×0.42 mm.对封装的传感器性能进行了初步测试,结果表明制作的传感器灵敏度约4.15 pF/g,品质因子为56,谐振频率为774 Hz.     

A Microfabricated Nebulizer for Liquid Vaporization in Chemical Analysis

A miniaturized nebulizer chip for vaporization of liquid samples for mass spectrometry has been designed, fabricated, and characterized for fluidic and thermal performance. Silicon/glass chip has a liquid sample channel placed centrally between symmetric nebulizer gas channels. The liquid sample is nebulized and vaporised by an integrated platinum heater. The vaporized sample exits through an etched nozzle, and is ionized by an external corona needle. The ions are analysed by a mass spectrometer. The chip has been fabricated in both anisotropically wet etched and DRIE versions in silicon, with an anodically bonded Pyrex glass cover plate. Three different fluidic inlet designs are presented, with both through-wafer and edge insert versions. The shape of the erupting gas jet has been visualized by infrared thermography by using a low-diffusivity imaging screen and high heat capacity helium as a test gas. Dimensions of the jet's thermal footprint on the screen show that the jet is very narrow and confined, and this is confirmed in mass spectrometry results. This confined jet supplies the sample to the ionization region near corona tip, enabling efficient use of very small sample amounts and submicroliter flows.1591     

Design,fabrication, and test of a peristaltic micropump

The design, fabrication, and electrical characterization of a novel peristaltic thermopneumatic microfluidic (PTMF) pump for next-generation implantable medical treatment. To satisfy the demands of an implantable system, the PTMF pump design presented here includes biocompatibility, simple integration with microfluidics, bidirectionality, and particle tolerance. Test devices were fabricated with both silicon micromachining and soft lithography (polydimethylsiloxane micromolding). The effects of process parameters, specifically those related to silicon wet etch and metal deposition, on the performance of the microheaters in a peristaltic microfluidic pump. The thermal resistance of the microheaters is strongly dependent upon the relative thermal isolation, which impacts maximum pumping speed (from a few Hertz to kilo-Hertz). Thermal isolation is shown not to be an issue in the pump design given the spacing of the neighboring microheaters.     

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-$mu$m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-$mu$m regime, while the only lithography step involved has$mu$m-scale resolution. This thick oxide mask layer with sub-$mu$m openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-$mu$m-thick oxide layer, while the original lithographically defined feature sizes are larger than 1$mu$m in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-$mu$m capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented.1684     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.