Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Formation of high quality storage capacitor dielectrics by in-siturapid thermal reoxidation of Si3N4 films inN2O ambient

This letter reports on a novel reoxidation technique for SiO₂ /Si₃N₄ (ON) stacked films by using N₂ O as oxidant. Effect of in-situ rapid thermal N₂O reoxidation (RTNO) on the electrical characteristics of thin ON stacked films are studied and compared with those of in-situ rapid thermal. O ₂ reoxidation (RTO). Prior to reoxidation, the Si₃N₄ film was deposited by rapid thermal chemical vapor deposition (RT-CVD) using SiH₄ and NH₃. Results show that RTNO of the Si₃N₄ films significantly improves electrical characteristics of ON stacked films in terms of lower leakage current, suppressed charge trapping, reduced defect density and improved time-dependent-dielectric-breakdown (TDDB), as compared to RTO of the Si₃N₄ films     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

Two silicon nitride technologies for post-SiO2 MOSFETgate dielectric

P-MOSFETs with 14 Å equivalent oxide thickness (EOT) were fabricated using both JVD Si₃N₄ and RTCVD Si₃ N₄/SiO_xN_y gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO₂ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large     

Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

A Program-Erasable High-κ Hf0.3N0.2O0.5 MIS Capacitor With Good Retention

We describe a programmable-erasable MIS capacitor with a single high-k Hf_0.3N_0.2O_0.5 dielectric layer. This device showed a capacitance density of ~6.6 fF/mum², low program and erase voltages of +5 and -5 V, respectively, and a large DeltaV_fb memory window of 1.5 V. In addition, the 25degC data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf_0.3N_0.2O_0.5.     

Novel capacitor process using diffusion barrier rounded by Si3N4 spacer for high density FRAM device

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si₃N₄ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si₃N₄ spacer before preparing Pb(Zr _1-xTi_x)O₃ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si₃N₄ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 Ω per contact with contact size 0.6×0.6 (μm²). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr_1-xTi_x)O₃ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2×1.2 (μm²) effective area displayed remnant polarization of 14 (μC/cm²) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125°C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125°C thermal stress     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Development of Embedded Three-Dimensional 35-nF/mm2 MIM Capacitor and BiCMOS Circuits Characterization

This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si₃N₄, Al₂O₃, Ta₂O₅ and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al₂O₃ deposited by ALD, high density of 35 nF/mm² is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (VCO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy₂O₃) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, V_t,lin of 0.18 V for long-channel devices (L_g = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy₂O₃ cap layer is also maintained in the short-channel devices (with an L_g,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy₂O₃ cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy₂O₃ layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

氮化硅集成微腔光频梳器件关键制备技术(特邀)

微腔光频梳,又称微腔梳,是通过腔内四波混频过程产生的一种高相干宽谱的集成光源,有着优异的时频特性,可用于超精密分子光谱、相干通信、激光雷达、轻型化装备等测量应用,是基础科学、计量学及军事装备的重要工具,是一项颠覆性的技术。报道了一种集成氮化硅（Si₃N₄）微腔光频梳器件制备的关键技术,提出了一种方法平衡Si₃N₄的应力、厚度和化学计量之间的矛盾,以满足反常色散和减少双光子吸收的要求。利用这种改进的大马士革工艺微结构降低Si₃N₄厚膜的应力,减少应力缺陷对器件性能的影响,实现高品质Si₃N₄薄膜的可控制备。在微腔刻蚀工艺中,采用30 nm氧化铝牺牲层补偿掩模抗刻蚀能力,实现微环和波导侧壁粗糙度小于15 nm,满足了微腔高Q值的要求。经双光泵浦测量得到1 480~1 640 nm波段内的宽光谱高相干克尔光频梳。     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

GaAs metal insulator field effect transistors with excellentintrinsic transconductance and stable drain currents using (NH4)2Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si₃N₄) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH₄)₂S_x. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D_it) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si ₃N₄ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 Å. Stability of the drain currents in these devices is demonstrated to be excellent     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells