Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

Scaling of MOS technology to submicrometer feature sizes

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.     

Scaling of MOS technology to submicrometer feature sizes

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

Analysis and control of floating-body bipolar effects in fullydepleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible     

Effects of high field injection on the hot carrier induceddegradation of submicrometer pMOSFET's

The interaction between the hot carrier (HC) induced pMOSFET's degradation and the Fowler-Nordheim (FN) injection is investigated. It has been found that the FN injection is an efficient method to recover pMOSFET's from the HC induced degradation. This is achieved by removing some of the trapped electrons from the oxide and forming positive charges along the channel. The relative importance of these two factors is determined. The contribution of the interface states created by FN injection is negligible, since they are acceptor-like and not charged during pMOSFET's operation. The positive charges increase the lifetime of a recovered pMOSFET by requiring more electron trapping to compensate their effects on the threshold voltage. They also enhance the magnitude of punchthrough voltage. The effects of FN injection on the HC trapping kinetics are discussed. Under our experimental conditions, the new trapping sites created by FN injection are negligible, compared with the as-grown traps. When a recovered pMOSFET is stressed again, its degradation rate is not higher than that of a fresh pMOSFET. This allows FN injection to be used repeatedly and we can therefore control the pMOSFET's degradation within a given range     

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.     

Scaling issues in chemical and biological sensors

When a system is reduced isomorphically in size (i.e., scaled down with all dimensions of the system decreased uniformly, or isomorphic scale reduction), the changes in length, area, and volume ratios alter the relative influence of various physical effects that determine the overall operation - often in unexpected ways. As objects shrink, the ratio of surface area to volume increases, rendering surface forces more important. More generally, as the size of an object decreases, forces scaling with a lower power of the linear dimension dominate over the ones scaling with a higher power (e.g., surface tension gains over gravity, electrostatics over magnetics, etc.) [see M. J. Madou, Fundamentals of Microfabrication, 2nd ed. (Boca Raton, FL: CRC, 2002)]. In this paper, we are investigating the influence of miniaturization on various aspects of chemical and biological sensors; we review scaling issues faced in sensor construction, the importance of sample size and the effect of sensor size on detection sensitivity in some of the most popular sensing approaches.     

Design criteria for GaAs MESFETs related to stationary high field domains

Using a modified theory of the high-field domains which takes into account the field-dependent diffusion we show that the existence of the high-field domain at drain side of the gate in GaAs MESFETs leads to a new set of design criteria which should be met to achieve the optimum performance. We derive these criteria and estimate the drain-to-source breakdown voltage and the maximum power of the device as functions of the doping density and device dimension. We also estimate the optimum gate length, the thickness of the active layer, the drain-to-gate separation and the doping level as functions of frequency. It is demonstrated that a larger than conventional drain-to-gate separation might be necessary for power devices to house a fully developed highfield domain and to avoid a premature breakdown at the drain. Our estimates indicate that the maximum power at 10 GHz can reach a theoretical limit of about 20 watts for class A operation.     

Backgating in submicrometer GaAs MESFET's operated at high drainbias

GaAs 0.8-μm MESFETs were seen to exhibit an increased sensitivity to backgating when operated at drain voltages above 3.5 V. This is accompanied by an abrupt increase in the DC output conductance (kink effect) and an increase in the current flowing in the back-gate electrode. It is proposed that the increased sensitivity to backgating is due to the injection of holes, from the high-field region of the channel, into the semi-insulating substrate. The results suggest that conventional layout rules may not always be sufficient to avoid backgating in circuits based in submicrometer GaAs MESFETs     

Ultraquasi-hydrodynamic electron transport in submicrometer field effect MIS transistors and heterotransistors

It is shown that electrons in the channel of submicrometer field effect transistors have no time to be heated to quasi-steady-state temperatures corresponding to a balance between the Joule heating and thermal relaxation. This “underheating” contributes to an increase in the effective mobility of charge carriers as compared to the value of μ(E) corresponding to the drift-diffusion approximation. Using a reduction of the thermal-balance equation by eliminating the relaxation-related term, a simple analytical expression is obtained for current-voltage characteristics. In particular, the saturation current in the developed ultraquasi-hydrodynamic model is found to be proportional to (V _G -V _t ) ^3/2 . The results of measurements of characteristics of the test GaAlAs/InGaAs/GaAs P-HEMTs with the channel length of about 0.3 μm are reported; these results verify the adequacy of the developed model, the accuracy of which can only increase with a further decrease in the channel length. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 34, No. 2, 2000, pp. 239–242. Original Russian Text Copyright ? 2000 by Gergel’, Mokerov, Timofeev, Fedorov.     

MOSFET's with PolySilicon gates self-aligned to the field isolation and to the source and drain regions

The fabrication procedure and device characteristics of MOSFET's having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. Another novel feature of this "recessed-gate" device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET's fabricated using more conventional methods, smaller FET's with increased packing density result from this misregistration-tolerant contacting technique and the doubly self-aligned gate electrode structure. The new FET structure may be applied to various integrated circuits such as ROM's, PLA's, and dynamic RAM's. The use of a second layer of polysilicon and the addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused storage region.     

Circuit related issues due to radiation in hostile environments

Various types of radiation in hostile environments cause transient and permanent changes in the devices used in complex integrated circuits. The failure of a particular IC is a function not only of the basic material and device parameter changes but also of the circuit environment in which the device is located. Circuit techniques have been developed which minimize the detrimental effects of radiation on certain types of circuits. In other cases, circuit techniques are not very effective in minimizing radiation effects. This work discusses selected issues related to the interactions between device radiation effects and circuit performance or circuit failure in a hostile radiation environment. This is not meant to be a comprehensive study of circuit effects but rather several examples are selected to illustrate the issues involved in designing circuits to operate in hostile radiation environments.     

Direct observation of the gate Oxide electric field distribution in Silicon MOSFET's

The charge collected within the SiO2layer of an MOS capacitor during bombardment with kilovolt electrons is approximately proportional to the field in the oxide. We have used this proportionality to form SEM images of the field distribution in MOSFET channels.     

关于公众对讲机管理有关问题的通知

为满足社会公众对使用民用低功率无线对讲机（以下称公众对讲机）的需求，同时防止对广播电视、导航、移动通信及射电天文等相关无线电业务产生有害干扰，确保各种无线电业务的有序开展，现就公众对讲机管理有关问题通知如下： 一、公众对讲机是指发射功率不大于０．５Ｗ，工作     

An analytical model for the channel electric field in MOSFET's with graded-drain structures

A simple analytical model for the lateral channel electric field in the drain region of MOSFET's with graded-drain or lightly doped drain structures is presented. The model's results agree well with two-dimensional simulations of the electric field in the drain region. Due to its simplicity, this model gives a better understanding of the mechanisms involved in reducing the electric field in the lightly doped region. Results show the impact of the length and doping concentration, assumed to be Gaussian, of the lightly doped region on the electric field. Effects of the oxide thickness and junction depth are also accounted for. In each case, there is an optimum doping concentration that minimizes the peak electric field.     

Carrier transport and related phenomena in MOS devices

Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO₂ barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I–V simulations, we have shown that the traps in SiO₂ matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I–V dependence with trap parameters.