基于低成本FPGA的AES密码算法设计

主要介绍在逻辑资源少的现场可编程门阵列（FPGA）上实现高级数据加密标准（AES）算法设计。首先描述了AES加密算法,并在FPGA上优化实现AES算法,设计结构采用多轮加密共用一个轮运算的顺序结构,加密和解密模块共用密钥扩展模块,减少资源占用,在低时钟频率下保持较高的性能。采用了16位的并行总线通信接口,利用先进先出缓冲器（FIFO）对输入输出数据进行缓存。最后通过仿真和实测表明,在50MHz时钟下加解密速率可达530Mb/s。     

嵌入式AES加密存储器的硬件实现

本设计主要介绍一种基于FPGA的AES硬件加密系统,实现电子数据的加密及存储。文中详细说明了AES加密算法的FPGA架构,AES核心算法的接口时序设计,AES加密存储器的硬件设计以及算法验证。硬件加密较之软件加密有实时性高、数据量大以及性能好的特点。FPGA开发周期短的特点与AES灵敏性好、实现效率高、安全性能高的优势相辅相成,为需要保密的电子数据提供更加可靠的保证。     

基于AES算法的加密模块设计

文中介绍了高级加密算法(AES)的基本原理,并给出了基于AES算法硬件加密模块设计方案.通过Modelsim6.le对其进行仿真实现,仿真结果表明,该加密模块能够很好的实现AES算法.     

AES算法的密码分析与快速实现

高级加密标准(AES)确定分组密码Rijndael为其算法,取代厂泛使用了20多年的数据加密标准(DES),该算法将在各行业各部门获得广泛的应用.文章以DES为参照对象,阐述了Rijndael算法的设计特色,介绍了AES在密码分析方面国内外已有的一些理论分析成果,描述了AES算法采用软件和硬件的快速实现方案.     

基于AMBA总线的AES算法设计

描述了基于AMBA（高级微控制器总线架构）总线的AES（高级加密标准）算法硬件设计。AES算法采用状态机实现,具有4种工作模式、支持2种密钥以及AHB（高级高性能总线）。采用实验室的SEGPS平台对设计进行仿真验证,并与采用C＋＋语言实现的AES进行比对验证。最后,选用FPGA（现场可编程门阵列）进行综合,结果显示,可工作最高频率为140．1MHz,占用逻辑单元的资源为6977,数据吞吐率最高为351．65Mbit／s。     

AES密码算法的FPGA优化设计

主要介绍基于FPGA的AES算法优化设计.从AES加密算-法的介绍、Rijndael算法的描述、AES密码算法的优化设计、AES密码算法的FPGA实现、PC机与FPGA的通信设计等方面论述实现硬件加密的方法,手段、可行性和优越性;实现了基于FPGA技术的Rijndacl算法,并给出了相应的各种仿真波形和结果.     

AES加密算法在防空系统中的应用

在防空系统中，大量数据以明文形式存储于数据库和文件中。为了保障重要数据的安全性，需要对这些数据进行加密后再存储。讨论了数据库加密的方式和加密粒度，选择了高安全性能的AES算法作为加密算法。对AES算法的基本原理进行了介绍，并根据实际应用设计了加密／解密模块处理方法和流程。采用C＋＋语言实现了AES算法的动态链接库，应用到防空系统的数据库加密和配置文件加密中。实现结果表明，该方法具有较高的安全性能，同时又易于实现，具有良好的推广价值。     

具有多种工作模式的AES算法的VLSI实现

从结构和算法上对AES算法进行了分析和优化,在一个模块内集成了加密和解密功能,实现了AES算法的所有5种工作模式,使其能满足多种保密性应用的需求.仿真和综合结果表明,此设计结构较好的实现了面积与速度的折中.     

基于FPGA的AES算法芯片设计实现

高级加密标准(AES)集安全性、高效性、灵活性于一身,研究其硬件实现具有很重要的应用价值.本文针对AES分组密码算法的结构特点,讨论了AES算法FPGA实现的优势,重点分析了加/脱密模块的实现方案,最后给出在Quartus Ⅱ下的仿真实验结果.     

数字通信中RS码的Step-by-step译码算法及实现

文章讨论了在数字通信系统中RS码的Step-by-step译码算法,给出了算法的基本原理并在现场可编程门阵列(FPGA)上实现了RS(7,3)码的编译码,给出了实际仿真的效果图.结果表明,所设计的电路能够纠正7位接收符号中的任意两位错误.采用此算法避开了求解错误定位多项式,使译码过程得以简化,并提高了译码速度,且易于用大规模可编程器件实现.     

一种优化可配置的AES密码算法硬件实现

AES加密算法是下一代的常规加密算法，其将被广泛应用在政府部门和商业领域。本文首先介绍了AES加密算法．然后分析了其硬件实现的要点和难点，最后在Xilinx的FPGA VirtexII XC2V3000-4上对AES密码算法进行了实现和验证。本方案采用一种优化的非流水线加密解密数据路径；同时提出了一种新的可配置的动态密钥调度结构，使得该设计支持128、192和256比特的密钥；而且该设计可以配置AES的四种工作模式。实验的结果表明该设计比其它的设计具有更高的性能。     

WSNs中基于FPGA的AES-ECC新型加密系统

针对无线传感器网络的特点,提出一种适于FPGA实现的改进的AES-ECC混合加密系统。本方案采用AES模块对数据进行加密,用SHA-1加密算法处理数据得到数据摘要,用ECC加密算法实现对摘要的签名和对AES私钥的加密。各个算法模块采用并行执行的处理方式以提高运算效率。方案优化了AES加密模块的设计,在占用相对较少逻辑资源的同时提高了系统吞吐率,通过优化ECC乘法单元的设计,提高了数字签名生成和认证的速度,完全满足了无线传感器网络对于稳定性、功耗以及处理速度的要求,给数据传输的安全性提供了高强度的保障。     

防御零值功耗攻击的AES SubByte模块设计及其VLSI实现

 密码器件在执行高级加密标准(Advanced Encryption Standard,AES)时常以能量消耗方式泄漏密钥信息,为有效降低其与实际处理数据之间的相关性,该文提出一种具有防御零值功耗攻击性能的AES SubByte模块设计及其VLSI实现方案.首先,在分析GF(256)域求逆算法的基础上,采用关键模块复用的方法,提出一种更为有效的加法性屏蔽求逆算法;然后依此进一步得到一种新型的SubByte模块结构,实现在不影响对所有中间数据进行加法性屏蔽编码的同时,减少电路的芯片开销、提高电路的工作速度.实验结果表明,所设计的电路具有正确的逻辑功能.与传统SubByte模块比较,该设计的最高工作频率和面积都有较大的优化.     

High Definition Image Encryption Algorithm Based on AES Modification

In this article, a high-speed and highly restricted encryption algorithm is proposed to cipher high-definition (HD) images based on the modified advanced encryption standard (AES) algorithm. AES is a well-known block cipher algorithm and has several advantages, such as high-level security and implementation ability. However, AES has some drawbacks, including high computation costs, pattern appearance, and high hardware requirements. The aforementioned problems become more complex when the AES algorithm ciphers an image, especially HD images. Three modifications are proposed in this paper to improve AES algorithm performance through, decreasing the computation costs, decreasing the hardware requirements, and increasing the security level. First, modification was conducted using MixColumn transformation in 5 rounds instead of 10 rounds in the original AES-128 to decrease the encryption time. Security is enhanced by improving the key schedule operation by adding MixColumn transformation to this operation as second modification. In addition, to decrease the hardware requirements, S-box and Inv. S-box in the original AES are replaced by one simple S-box used for encryption and decryption in the proposed method. The proposed AES version conducts one of the ciphering modes to solve the appearance pattern problem. Experimental results indicate that the proposed modifications to the AES algorithm made the algorithm more compatible with HD image encryption.     

基于MIPS处理器的AES算法指令集扩展方法与实现

由于MIPS处理器数据总线宽度的限制,其扩展的AES(高等加密标准)指令集无法有效实现其并行性的特点.为了提高AES扩展指令集的并行处理能力,利用MIPS处理器中乘法结果寄存器.可以一次实现对64比特数据的AES处理,有效利用处理器自身资源提高指令集的并行处理能力.同时,利用MIPS处理器的空闲流水周期可以流水化AES中的关键运算,缩短其关键路径以降低扩展执行单元对流水周期的影响,对不同实现方式的性能进行比较,结果表明该方法缩短了AES算法中复杂运算的关键路径长度从而使处理器的工作频率不受增加的功能单元的影响,同时有效地减少了芯片面积,并且继承了软件编程灵活性的优点。     

AES Algorithm of Improving WPAN Throughput

The throughput of WPAN (Wireless Personal Area Network) based on Bluetooth was decided by the interference of Bluetooth piconets in the network. The interference was decided by the hamming correlation of Bluetooth FH (Frequency Hopping) selected sequence. In order to improve the WPAN throughput, the WPAN model and data packet collision model were built and the relations about WPAN throughput, the maximum hamming correlation of FH selected sequence, the numbers of Bluetooth piconets and the SNR of channel were analyzed. The functions of WPAN throughput were deduced. After analyzing the performance of Bluetooth FH selected sequence, the original algorithm was replaced by the AES (Advanced Encryption Standard) algorithm. The theoretical analysis proved that the AES FH sequences selected algorithm could improve the WPAN throughput. The simulation results proved the theoretical analysis. The test result with ARM926EJs SoC (System on Chip) + RF (Radio Frequency) chip nRF2401 and CSR??s Bluecore4 Bluetooth module got the same conclusion. All of these could prove that the AES algorithm can improve the WPAN throughput efficiently.     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

High-Throughput Area-Efficient Processor for Cryptography

Cryptography circuits for portable elec-tronic devices provide user authentication and secure data communication. These circuits should, achieve high per-formance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a high-performance ASIP (Application specific instruction set processor) for five standard cryptographic algorithms in-cluding both block ciphers (AES, Camellia, and ARIA) and stream ciphers (ZUC and SNOW 3G). The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2 (65 nm). Compared with state-of-the-art VLSI designs, our design achieves high perfor-mance, low silicon cost, low power consumption, and suf-ficient programmability. For its programmability, our de-sign can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.