A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A dual-mode transceiver integrates the transmitter of 0-dBm output power and the receiver for both Bluetooth with -87 dBm sensitivity and 802.11b with -86 dBm sensitivity in a single chip. A direct-conversion architecture enables the maximum reuse and the optimal current consumption of the various building blocks in each mode for a low-cost and low-power solution. A single-ended power-amplifer (PA) driver transmits the nominal output power of 0 dBm with 18-dB gain control in 3-dB steps. Only little area overhead is required in the baseband active filter and programmable gain amplifier (PGA) to provide the dual-mode capability with optimized current consumption. The DC-offset cancellation scheme coupled with PGAs implements the very low high-pass cutoff frequency with a smaller area than required by a simple coupling capacitor. Fabricated in 0.25-/spl mu/m CMOS process, the die area is 8.4 mm/sup 2/ including pads, and current consumption in RX is 50 mA for Bluetooth and 65 mA for 802.11b from a 2.7-V supply.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A CMOS 5 nV$/surd $Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 mum CMOS occupying 1.65 mm² is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an active-G_m-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 divide 68 dB, while the input-referred noise (IRN) is 5 nV/radicHz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-/spl mu/m CMOS

A fully integrated transceiver suitable for low-data-rate wireless telemetry and sensor networks operating in the license-free ISM frequency bands at 433, 868, or 915 MHz implemented in 0.25-/spl mu/m CMOS is presented. G/FSK, ASK, and OOK modulation formats are supported at data rates from 0.3 to 200 kb/s. The transceiver's analog building blocks include a low-noise amplifier, mixer, channel filter, received signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. FSK demodulation is implemented using a novel digital complex-frequency correlator that operates over a wide modulation-index range and approximates matched filter detection performance. Automatic gain control, automatic frequency control, and symbol timing recovery loops are included on chip. Operating in the 915-MHz band in FSK mode at 9.6 kb/s, the receiver consumes 19.7 mA from a 3-V supply and achieves a sensitivity of -112.8dBm at 0.1% BER. The transmitter consumes 28.5 mA for an output power of 10 dBm and delivers up to 14 dBm.     

CMOS linear programmable transconductor suitable for adjustable Gm-C filters

A novel CMOS linear programmable transconductor is presented. It is based on a telescopic cascode operational transconductance amplifier with source degeneration implemented by means of highly linear tunable active resistors. The transconductor has been designed in a 0.5 mum CMOS technology featuring a third-order intermodulation (IM3) of -54.8 dB at 10 MHz for a 1 V_pp output voltage. Its feasibility for Gm-C filter design has been experimentally validated with a 1 MHz tunable third-order Chebyshev lowpass filter suitable for Bluetooth applications.     

一种-16 dB ~12 dB增益范围的高线性度PGA设计

可编程增益放大器广泛应用于射频接收通道,起中频放大、驱动模数转换器的功能.基于电阻反馈运放设计的可编程增益放大器具有动态范围大、线性度高的特点.文中采用互补金属氧化物半导体工艺设计实现了一种基于全差分运放和衰减器的宽范围、高线性度可编程增益放大器.测试结果表明增益变化范围为-16dB～12dB,步进为1 dB,输出1 dB压缩点大于10 dBm@60 MHz,输出三阶交调点大于26 dBm@60 MHz.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A BFSK and OOK IF demodulation circuit with 2.8 μs settling time and re-configurable image rejection functions for MICS/BCC applications

A BFSK and OOK IF base-band circuit is provided to implement the low-IF RF receivers for a dualband MICS/BCC network controller.In order to transfer the massive vital data immediately,the IF circuit is comprised of the fast-settling feed-forward programmable gain amplifier (PGA),a Gm-C complex filter,the fixed gain amplifier (FGA) and a 4-input "quadratic sum" demodulator.A novel auto-switched coarse gain-setting method is adopted in the PGA to enhance the reaction speed and narrow the output signal range.Also the PGA does not suffer the same stability constraint as open-loop topologies.The complex filter fulfills the function of image rejection,in which the center frequency and bandwidth can be adjusted individually.The FGA is used to ameliorate the linearity and the 'quadratic sum' demodulator can reduce the overall power consumption.The designed IF circuit is fabricated with SMIC 0.18/μm CMOS process.The chip area is about 5.36 mm2.Measurement results are given to verify the design goals.     

A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications

A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF tuner IC using 0.18-/spl mu/m CMOS technology. An improvement of 13-dB IIP3 is attained without significant degradation of other performance criteria like gain, noise figure, common-mode rejection ratio, etc., at similar power consumption. This is achieved by applying a newly proposed differential circuit gm" (the second derivatives of transconductance) cancellation technique, called the differential multiple gated transistor (DMGTR). In the DMGTR amplifier, the negative value of gm" in the fully differential amplifier can be compensated by the positive value of gm" in the pseudo differential amplifier which is properly sized and biased. By adopting the DMGTR, a low-power highly linear RF PGA is implemented. Also, in order to have wide gain range with fine step resolution, a new RF PGA architecture is proposed. The measurement results of the proposed RF PGA exhibit 50-dB gain range with 0.25-dB resolution, 4.5-dB noise figure, a -4-dBm IIP3 (maximum 30 dBm) and 25-dB gain at 16-mW power consumption.     

A single-chip 2.4-GHz direct-conversion CMOS receiver for wirelesslocal loop using multiphase reduced frequency conversion technique

A single-chip direct-conversion CMOS receiver for 2.4-GHz wide-band code-division multiple-access wireless local loop (WLL) is described. The chip includes a low noise amplifier, a 12-phase downconverter, a variable gain amplifier, a g_m-C channel selection filter, a programmable phase-locked loop for seven channel frequencies, and a 4-bit flash analog-to-digital converter. The proposed multiphase reduced frequency conversion scheme combined with a multiphase sampling fractional-N prescaler, a cascaded dc-offset canceler and distributed automatic gain control loops offers solutions to problems of a direct-conversion receiver. Experimental results show -115-dBm sensitivity, 4.4-dB noise figure, and 95-dB dynamic range, which sufficiently meet commercial WLL specification     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

一种应用于CMOS图像传感器中的线性步进PGA设计

A low power linear stepping digital programming gain amplifier （PGA） is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.     

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.     

A CMOS bandpass filter for low-IF bluetooth receivers

A CMOS fully integrated 12th-order bandpass filter for low interemdiate frequency Bluetooth receivers is presented. The design is optimized to meet the selectivity and dynamic range requirements of Bluetooth while consuming relatively low power. The filter is based on unity gain cells and utilizes linearized MOSFET resistors for tuning. It exhibits a bandwidth of 1 MHz and a programmable center frequency range of 2 to 4 MHz. Experimental results obtained from a standard 0.5-/spl mu/m CMOS chip show that the filter exhibits an in-band dynamic range of 53.3 dB at gain of 0 dB, and 52 dB at gain of 15 dB, while consuming a total current of 1.32 mA. Attenuations of more than 10, 38, and 55 dB, are achieved for blockers one, two, and three, respectively.     

A linear stepping PGA used in CMOS image sensors

A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.