Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Interface-Charge-Coupled Polarization Response of Pt-BaTiO<Subscript>3</Subscript>-ZnO-Pt Heterojunctions: A Physical Model Approach

Heterojunctions composed of wurtzite-structure (piezoelectric) ZnO and perovskite-structure (ferroelectric) BaTiO₃ are very interesting because of the previously observed ionic lattice polarization coupling at their interfaces. We report electric Sawyer-Tower polarization hysteresis measurements and analysis of a ZnO-BaTiO₃ heterostructure with Pt front and back contacts deposited by pulsed laser deposition onto a (001) silicon substrate. The ZnO layer is n-type (N _c = 5.5 × 10¹⁶ cm⁻³), and the BaTiO₃ (BTO) layer is highly resistive. We observe a strong asymmetric ferroelectric hysteresis, which we attribute to a rectifying depletion layer formation between the ZnO and BaTiO₃ layers. The coupling between the wurtzite-structure and perovskite-structure interface polarization influences the depletion layer formation. We develop a physical model for the electric Sawyer-Tower measurements. Our model includes the effects of the depletion layer formation inside the ZnO layer, the interface charge coupling between the ZnO and BaTiO₃ layers, and the field-dependent ferroelectric polarization inside the BTO. We obtain a very good agreement between our model-generated data and our experiment. We identify voltages in forward and reverse direction at which the depletion layer opens or closes. These voltages are asymmetric, and reveal the effect of the spontaneous piezoelectric (nonswitchable) interface charge of ZnO, which we determine from our analysis here as P _sz = −4.1 μC/cm².     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Electrical characterization of metal-oxide-high-k dielectric-oxide-semiconductor (MOHOS) structures for memory applications

Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal-oxide-high-k dielectric-oxide-silicon (MOHOS) structures are fabricated using HfO₂ and Dy₂O₃ high-k dielectrics as the charge storage layer. The Al/SiO₂/Dy₂O₃/SiO₂/Si capacitors have a C–V memory window of 1.88 V and a leakage current density of 10⁻⁸ A/cm². This leakage current is lower than those of Al/SiO₂/HfO₂/SiO₂/Si capacitors and other similar capacitors reported in the literature. A minimum detection window of 0.5 V for MOHOS capacitors can be maintained up to 2 × 10⁸ s using as-deposited Dy₂O₃. The better performance of the Al/SiO₂/Dy₂O₃/SiO₂/Si structure over Al/SiO₂/HfO₂/SiO₂/Si is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface (2.3 eV) versus 1.6 eV at the HfO₂/SiO₂ interface.     

Low-Temperature Pulsed-PECVD ZnO Thin-Film Transistors

We report high-quality ZnO thin films deposited at low temperature (200°C) by pulsed plasma-enhanced chemical vapor deposition (pulsed PECVD). Process byproducts are purged by weak oxidants N₂O or CO₂ to minimize parasitic CVD deposition, resulting in high-refractive-index thin films. Pulsed-PECVD-deposited ZnO thin-film transistors were fabricated on plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ dielectric and have a field-effect mobility of 15 cm²/V s, subthreshold slope of 370 mV/dec, threshold voltage of 6.6 V, and current on/off ratio of 10⁸. Thin-film transistors (TFTs) on thermal SiO₂ dielectric have a field-effect mobility of 7.5 cm²/V s and threshold voltage of 14 V. For these devices, performance may be limited by the interface between the ZnO and the dielectric.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr₂O₃) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10⁻⁶ A/cm² have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr₂O₃ surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.     

Optical and electrical characterization of hafnium oxide deposited by liquid injection atomic layer deposition

Optical and electrical properties of a set of high-k dielectric HfO₂ films, deposited by liquid injection atomic layer deposition (LI-ALD) and post deposition annealed (PDA) in nitrogen (N₂) ambient at various temperatures (400–600 °C), were investigated. The films were prepared using the cyclopentadienyl of hafnium precursor [Cp₂Hf(CH₃)₂] with water deposited at 340 °C. The spectroscopic ellipsometric (SE) results show that the characteristics of the dielectric functions of these films are strongly affected by annealing temperatures. I–V results show that N₂-based PDA enhances the average energy depth of the shallow trapping defects from Poole–Frenkel conduction fitting. This also correlated with the measured increase in MOS capacitance–voltage hysteresis.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Flexible complementary inverter with low-temperature processable polymeric gate dielectric on a plastic substrate

We report low-temperature processability of poly(4-vinylphenol) based gate dielectric by investigating the effect of composition and processing temperature on the thermal, mechanical and electrical characteristics of the gate dielectric. We found that the processing temperature of the gate dielectric could be reduced up to 70 °C by optimizing the composition of the gate dielectric solution. Based on this finding, we have fabricated a flexible organic complementary inverter by integrating n- and p-type organic thin-film transistors (OTFTs) with the low-temperature processable gate dielectric on a plastic substrate. Pentacene and F16CuPc were used as p-type and n-type semiconductor, respectively. The inverter shows that the swing range of V_out is same as V_DD, which ensures “zero” static power consumption in digital circuits. The logic threshold of the inverter with G5 gate dielectric cured at 70 °C is 21.0 V and the maximum voltage gain (∂V_out/∂V_in) of 8.1 is obtained at V_in = 21.0 V. In addition, we have discussed in more detail the characteristics of the OTFTs and the complementary inverter with respect to the process condition of the gate dielectric.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

Charge trapping in ultrathin Gd2O3 high-k dielectric

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10⁻²⁰ cm². The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 10¹² eV⁻¹ cm⁻² near the valence band edge.     

Spectroscopic ellipsometry characterization of ZrO2 thin films by nitrogen-assisted reactive magnetron sputtering

Spectroscopic ellipsometry (SE) with photon energy 0.75–6.5 eV at room temperature has been used to derive the optical properties of high-k ZrO₂ thin films on Si(1 0 0) substrates prepared by nitrogen-assisted, direct current reactive magnetron sputtering. The Tauc–Lorentz dispersion method was adopted to model the optical dispersion functions of the thin films as a function of annealing temperature. Excellent agreement has been found between the SE fitting results and X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and Fourier transform infrared spectroscopy (FTIR) results, indicating that our model adequately described the measured SE data. Optical band gaps (E_g) were also obtained based on the extracted absorption edge. Our results suggest that nitrogen-assisted process can effectively limit the interfacial layer growth in high-k oxides.     

Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

Thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N₂ anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeO_x, the wet-N₂ anneal can greatly suppress the growth of unstable low-κ GeO_x interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N₂ ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 10¹¹ eV⁻¹ cm⁻² and gate leakage current of 5.7 × 10⁻⁴ A/cm² at V_g = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N₂ ambient.     

Catalyst-Free Direct Vapor-Phase Growth of Hexagonal ZnO Nanowires on <Emphasis>α</Emphasis>-Al<Subscript>2</Subscript>O<Subscript>3</Subscript>

The evolution of ZnO nanowires has been studied under supersaturation of Zn metal species with and without a ZnO thin-film buffer layer on α-Al₂O₃ deposited by the pulsed laser ablation technique. The nanowires had diameters in the range of 30 nm to 50 nm and lengths in the range of 5 μm to 10 μm with clear hexagonal shape and [000[`1]] [000\bar{1}] , [10[`1]1] [10\bar{1}1] , and [10[`1]0] [10\bar{1}0] facets. X-ray diffraction (XRD) measurements indicated crystalline properties for the ZnO nanostructures grown on pulsed laser deposition (PLD) ZnO nucleation layers. The optical properties were analyzed by photoluminescence (PL) and cathodoluminescence (CL) measurements. The ZnO nanowires were found to emit strong ultraviolet (UV) light at 386 nm and weak green emission as observed by PL measurements. The stoichiometry of Zn and O was found to be close to 1 by x-ray photoelectron spectroscopy (XPS) measurements. The process-dependent growth properties of ZnO nanostructures can be harnessed for future development of nanoelectronic components including optically pumped lasers, optical modulators, detectors, electron emitters, and gas sensors.